Abstract: In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.

Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.

Abstract: A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.

Abstract: A method of manufacturing a polarizing glass sheet includes subjecting, while heating, a glass preform sheet containing metal halide particles to down-drawing, to thereby provide a glass member having stretched metal halide particles dispersed in an aligned manner in a glass matrix, and subjecting the glass member to reduction treatment to reduce the stretched metal halide particles, to thereby provide a polarizing glass sheet. A shape of the glass preform sheet during the down-drawing satisfies a relationship of the following expression: L1/W1?1.0 where L1 represents a length between a portion in which a width of the glass preform sheet has changed to 0.8 times an original width and a portion in which the width of the glass preform sheet has changed to 0.2 times the original width W0, and W1 represents a length equivalent to 0.5 times the original width W0 of the glass preform sheet.

Abstract: The packet processing apparatus includes a packet memory, a transmission processing unit that writes a plurality of packets to be transmitted to the packet memory to generate a combination packet into which the plurality of packets have been concatenated, a line handling unit that sends packets to a communication line, and a combination packet transfer unit that DMA-transfers the combination packet from the packet memory to the line handling unit. The transmission processing unit writes information on an address in the packet memory of beginning data of an individual packet in the combination packet to a descriptor. The line handling unit separates the DMA-transferred combination packet into a plurality of packets and sends the plurality of packets to the communication line.

Abstract: A packet processing apparatus includes a packet processor that performs processing on a packet received from a communication line and outputs data that is a result of the processing, a data combiner that concatenates a plurality of pieces of data output from the packet processor to generate a data block, and a combination data transferor that DMA-transfers the data block generated by the data combiner to a data memory. The combination data transferor writes information on an address in the data memory of a beginning of an individual piece of data in the data block to a descriptor that is a data area on a predetermined memory.

Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Abstract: A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.

Abstract: A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.

Abstract: In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.

Abstract: An OLT (10) is provided with a priority control bypass circuit (16) and an encryption/decryption bypass circuit (17), or an ONU (20) is provided with a priority control bypass circuit (26) and an encryption/decryption bypass circuit (27), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

Abstract: A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

Abstract: A packet processing device includes: a line adapter configured to receive packets from a communication line; a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line; a packet memory configured to store packets received from the communication line; and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit writes information of an address of first data of each packet inside the combined packet on the packet memory into a descriptor that is a data area on a memory set in advance.

Abstract: An upstream allocation circuit (14) and a downstream allocation circuit (15) are provided in an OLT (1). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit (14) via a frame reproduction circuit (12-1). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit (14) allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit (13) based on information (PON port number or LLID) added to the frames. The downstream allocation circuit (15) allocates, to a preset frame reproduction circuit (12), each downstream control frames output from the PON control circuits (13).

Abstract: An OLT (10) is provided with a priority control bypass circuit (16) and an encryption/decryption bypass circuit (17), or an ONU (20) is provided with a priority control bypass circuit (26) and an encryption/decryption bypass circuit (27), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

Abstract: A method of manufacturing a polarizing glass sheet includes subjecting, while heating, a glass preform sheet containing metal halide particles to down-drawing, to thereby provide a glass member having stretched metal halide particles dispersed in an aligned manner in a glass matrix, and subjecting the glass member to reduction treatment to reduce the stretched metal halide particles, to thereby provide a polarizing glass sheet. A shape of the glass preform sheet during the down-drawing satisfies a relationship of the following expression: L1/W1?1.0 where L1 represents a length between a portion in which a width of the glass preform sheet has changed to 0.8 times an original width and a portion in which the width of the glass preform sheet has changed to 0.2 times the original width W0, and W1 represents a length equivalent to 0.5 times the original width W0 of the glass preform sheet.

Abstract: A method of manufacturing a polarizing glass sheet includes subjecting, while heating, a glass preform sheet containing metal halide particles to down-drawing, to thereby provide a glass member having stretched metal halide particles dispersed in an aligned manner in a glass matrix, and subjecting the glass member to reduction treatment to reduce the stretched metal halide particles, to thereby provide a polarizing glass sheet. A shape of the glass preform sheet during the down-drawing satisfies a relationship of the following expression: L1/W1?1.0 where L1 represents a length between a portion in which a width of the glass preform sheet has changed to 0.8 times an original width and a portion in which the width of the glass preform sheet has changed to 0.2 times the original width W0, and W1 represents a length equivalent to 0.5 times the original width W0 of the glass preform sheet.

Abstract: A selection and distribution circuit (13) is provided between N optical transceivers (11) and one PON control circuit (12). The selection and distribution circuit (13) selects the optical transceiver (11) corresponding to an upstream frame that time-divisionally arrives, thereby transferring the upstream frame opto-electrically converted by the transceiver (11) to the PON control circuit (12) and distributing a downstream frame from the PON control circuit (12) to each optical transceiver (11). A power supply control circuit (23) stops power supply to at least one of one of optical transceivers (11) that are not used to transfer the frame of the optical transceivers (11) and a circuit that is not used to transfer the frame in the selection and distribution circuit (13). This can reduce the system cost per ONU in the optical transmission system.

Abstract: An upstream allocation circuit (14) and a downstream allocation circuit (15) are provided in an OLT (1). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit (14) via a frame reproduction circuit (12-1). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit (14) allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit (13) based on information (PON port number or LLID) added to the frames. The downstream allocation circuit (15) allocates, to a preset frame reproduction circuit (12), each downstream control frames output from the PON control circuits (13).

Abstract: A cam follower is constituted by an outer ring which has an outer track surface in its inner circumference; a stud which has an inner track surface opposed to the outer track surface, a flange portion abutting on one side of the inner track surface, a side plate fitting portion and a mounting shaft portion abutting on another side of the inner track surface in this order, and a fiber flow formed continuously from the flange portion to the inner track surface along their outer circumferences; rolling elements which are arranged between the outer track surface and inner track surface; and an inner side plate which is pressed into the side plate fitting portion to work with the flange portion for limiting axial movement of the outer ring and the rolling elements.