Patents by Inventor Tomoaki Kudaishi

Tomoaki Kudaishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7995984
    Abstract: The present invention aims to reduce an exclusively-possessed area of each of bonding wires mounted over a wiring board, for coupling a power amplifying unit of a semiconductor chip and an antenna switch of a second semiconductor chip in a semiconductor device that configures an RF module. In the RF module, the first semiconductor chip and the second semiconductor chip are mounted side by side in a central area of the wiring board. The first semiconductor chip is formed with amplifier circuits and a control circuit and comprises a silicon substrate or a compound semiconductor substrate. On the other hand, the second semiconductor chip is formed with an antenna switch and comprises the silicon substrate or compound semiconductor substrate. Pads of the first semiconductor chip and pads of the second semiconductor chip are respectively electrically coupled to one another.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoaki Kudaishi, Satoshi Sakurai, Takayuki Tsutsui, Masashi Yamaura, Reiichi Arai, Takayuki Maehara
  • Patent number: 7962105
    Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: June 14, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Sato, Nobuyoshi Maejima, Tomoaki Kudaishi, Shinji Moriyama, Naoki Kuroda, Ryota Sato, Masashi Okano
  • Publication number: 20100178879
    Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Yusuke Sato, Nobuyoshi Maejima, Tomoaki Kudaishi, Shinji Moriyama, Naoki Kuroda, Ryota Sato, Masashi Okano
  • Patent number: 7706756
    Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: April 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yusuke Sato, Nobuyoshi Maejima, Tomoaki Kudaishi, Shinji Moriyama, Naoki Kuroda, Ryota Sato, Masashi Okano
  • Publication number: 20090130996
    Abstract: The present invention aims to reduce an exclusively-possessed area of each of bonding wires mounted over a wiring board, for coupling a power amplifying unit of a semiconductor chip and an antenna switch of a second semiconductor chip in a semiconductor device that configures an RF module. In the RF module, the first semiconductor chip and the second semiconductor chip are mounted side by side in a central area of the wiring board. The first semiconductor chip is formed with amplifier circuits and a control circuit and comprises a silicon substrate or a compound semiconductor substrate. On the other hand, the second semiconductor chip is formed with an antenna switch and comprises the silicon substrate or compound semiconductor substrate. Pads of the first semiconductor chip and pads of the second semiconductor chip are respectively electrically coupled to one another.
    Type: Application
    Filed: October 3, 2008
    Publication date: May 21, 2009
    Inventors: Tomoaki Kudaishi, Satoshi Sakurai, Takayuki Tsutsui, Masashi Yamaura, Reiichi Arai, Takayuki Maehara
  • Patent number: 7420284
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Publication number: 20070210866
    Abstract: A technique is provided for achieving reduction in size of an electronic device with a power amplifier circuit, while enhancing the performance of the electronic device. An RF power module for a mobile communication device includes first and second semiconductor chips, a passive component, and first and second integrated passive components, which are mounted over a wiring board. In the first semiconductor chip, MISFET elements constituting power amplifier circuits for the GSM 900 and for the DCS 1800 are formed, and a control circuit is also formed. In the first integrated passive component, a low pass filter circuit for the GSM 900 is formed, and in the second integrated passive component, a low pass filter circuit for the DCS 1800 is formed. In the second semiconductor chip, antenna switch circuits for the GSM 900 and DCS 1800 are formed. Over the upper surface of the wiring board, the second semiconductor chip is disposed next to the first semiconductor chip between the integrated passive components.
    Type: Application
    Filed: January 24, 2007
    Publication date: September 13, 2007
    Inventors: Yusuke Sato, Nobuyoshi Maejima, Tomoaki Kudaishi, Shinji Moriyama, Naoki Kuroda, Ryota Sato, Masashi Okano
  • Patent number: 7223636
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: May 29, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Publication number: 20070105283
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 10, 2007
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Publication number: 20060261494
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: July 25, 2006
    Publication date: November 23, 2006
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Patent number: 7091620
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Grant
    Filed: April 28, 2005
    Date of Patent: August 15, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Akita Electronics Systems, Co., Ltd.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Publication number: 20050212142
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 29, 2005
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Publication number: 20050200019
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: April 28, 2005
    Publication date: September 15, 2005
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Publication number: 20050167808
    Abstract: A semiconductor device comprising a semiconductor chip having an electrode on a circuit formation surface thereof, a flexible film having a lead attached thereto and electrically connected to said electrode of said semiconductor chip through a bump, a resin for covering said circuit formation surface of said semiconductor chip and a resin film for covering a back surface facing said circuit formation surface of said semiconductor chip.
    Type: Application
    Filed: March 30, 2005
    Publication date: August 4, 2005
    Inventors: Masako Sasaki, Kazunari Suzuki, Seiichi Ichihara, Tomoaki Kudaishi, Hisao Nakamura, Kunihiko Nishi, Hideki Tanaka, Yutaka Nakajima
  • Publication number: 20050101052
    Abstract: In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.
    Type: Application
    Filed: October 12, 2004
    Publication date: May 12, 2005
    Inventors: Yoshihiko Kobayashi, Susumu Sato, Koki Tanimoto, Tomio Yamada, Hirokazu Nakajima, Tomoaki Kudaishi, Yoshinori Shiokawa, Toshiharu Niitsu, Tsutomu Ida
  • Patent number: 6875631
    Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: April 5, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Sanwa Denki Kogyo Co., Ltd.
    Inventors: Hirotaka Nishizawa, Hideki Tanaka, Yuichiro Yamada, Tomoaki Kudaishi, Akira Katsumata
  • Patent number: 6759754
    Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: July 6, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Sanwa Denki Kogyo Co., Ltd.
    Inventors: Hirotaka Nishizawa, Hideki Tanaka, Yuichiro Yamada, Tomoaki Kudaishi, Akira Katsumata
  • Publication number: 20040061220
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Application
    Filed: February 28, 2003
    Publication date: April 1, 2004
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe, Takehiro Ohnishi, Noriou Shimada, Shuji Eguchi, Hiroshi Koyama, Akira Nagai, Masahiko Ogino
  • Patent number: 6670215
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: December 30, 2003
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Patent number: 6664135
    Abstract: A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.
    Type: Grant
    Filed: January 30, 2002
    Date of Patent: December 16, 2003
    Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masanori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe