Abstract: An image processing apparatus (encoder, decoder or the like) and method suppress reduction in encoding efficiency. Encoding of coefficient data is skipped in an invalid transform coefficient region, and the coefficient data is encoded in a valid transform coefficient region. Further, for example, the coefficient data in the valid transform coefficient region is encoded in a scan order corresponding to a block shape of a block to be processed. In addition, decoding of encoded data including encoded coefficient data related to an image is skipped in an invalid transform coefficient region, and the encoded data is decoded in a valid transform coefficient region. Further, for example, the encoded data in the valid transform coefficient region is decoded in a scan order corresponding to the block shape of the block to be processed.

Abstract: An image processing apparatus (encoder, decoder or the like) and method suppress reduction in encoding efficiency. Encoding of coefficient data is skipped in an invalid transform coefficient region, and the coefficient data is encoded in a valid transform coefficient region. Further, for example, the coefficient data in the valid transform coefficient region is encoded in a scan order corresponding to a block shape of a block to be processed. In addition, decoding of encoded data including encoded coefficient data related to an image is skipped in an invalid transform coefficient region, and the encoded data is decoded in a valid transform coefficient region. Further, for example, the encoded data in the valid transform coefficient region is decoded in a scan order corresponding to the block shape of the block to be processed.

Abstract: A data stream inputted to the inventive system from the outside is supplied to a PID (packet ID) extracting circuit 1, in which a PID is detected from a transport stream TS regardless of whether the transport stream TS is a full transport stream TS or a partial transport stream TS. The PID extracting circuit 1 transmits the thus extracted PID and data stream to a TS replacing/deleting circuit 2. The TS replacing/deleting circuit 2 has n 188-byte buffers and is able to set replaced TS packets to the buffers. A control circuit 3 such as a CPU (central processing unit) designates m PIDs relative to the respective buffers and designates the respective PIDs as the PID of the packet to be deleted or the PID of the packet to be replaced. Then, the TS replacing/deleting circuit 2 compares the PID received from the PID extracting circuit 1 with the PID designated by the control circuit 3.

Abstract: A data stream inputted to the inventive system from the outside is supplied to a PID (packet ID) extracting circuit 1, in which a PID is detected from a transport stream TS regardless of whether the transport stream TS is a full transport stream TS or a partial transport stream TS. The PID extracting circuit 1 transmits the thus extracted PID and data stream to a TS replacing/deleting circuit 2. The TS replacing/deleting circuit 2 has n 188-byte buffers and is able to set replaced TS packets to the buffers. A control circuit 3 such as a CPU (central processing unit) designates m PIDs relative to the respective buffers and designates the respective PIDs as the PID of the packet to be deleted or the PID of the packet to be replaced. Then, the TS replacing/deleting circuit 2 compares the PID received from the PID extracting circuit 1 with the PID designated by the control circuit 3.

Abstract: A disk data reproducing apparatus and a disk data reproducing method for carrying out error correction at fixed intervals independent of demodulation rate fluctuations caused by variable disk revolutions during access, whereby the reliability of error correction is improved. Data are demodulated by use of a regenerative clock signal acquired in keeping with the input data rate, whereas error correction is conducted at a fixed frequency clock signal. Two counters are provided, one being incremented by a signal generated upon detection of a block top, the other counter being incremented by a signal generated when a block of erroneous data is corrected. The two computers are compared in contents so that depending on the result of the comparison, an error correction start signal is generated. Error correction is performed always at fixed intervals regardless of the velocity of reproduction being standard, doubled, quadrupled, or multiplied by a factor of j (j: natural number).