Patents by Inventor Tomoaki Maeda

Tomoaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7777663
    Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Patent number: 7619550
    Abstract: In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: November 17, 2009
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Maeda, Taiji Akizuki, Hisashi Adachi
  • Patent number: 7532138
    Abstract: In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: May 12, 2009
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Tomoaki Maeda, Masahiko Sagisaka
  • Publication number: 20090115523
    Abstract: The present invention is intended to attain simplified circuit configuration and low current consumption in a discrete time amplifier circuit and an AD converter, to improve the convergence from the transient response state to the steady state of the amplifier circuit and to reduce noise and distortion owing to the variation in the output common-mode voltage. The discrete time amplifier circuit and the AD converter are provided with a switched-capacitor common-mode feedback (CMFB) circuit capable of detecting and feeding back the output common-mode voltage at every sampling timing in the case that the circuit operates at double sampling timing (every ½ cycle).
    Type: Application
    Filed: October 30, 2008
    Publication date: May 7, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Taiji AKIZUKI, Tomoaki Maeda, Hisashi Adachi
  • Patent number: 7515080
    Abstract: An A/D converter includes a first switched capacitor block that charges and holds charges by connecting each of a first group of capacitors to a single basic reference voltage at a first timing, and discharges each of the charges held by the first group of capacitors at a second timing, a second switched capacitor block that charges and holds each of the charges discharged by the first group of capacitors respectively in the second group of capacitors at the second timing, and converts each of the charges held by the second group of capacitors to a voltage and outputs the voltages at the first timing, and a quantizer that quantizes an analog input signal using the plurality of voltages output from the second switched capacitor block as reference voltages for each level. A plurality of reference voltages is generated from a single basic reference voltage, based on different amounts of charges held in the plurality of capacitors.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: April 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Patent number: 7515079
    Abstract: To provide a method of controlling a delta-sigma modulator and a delta-sigma modulator capable of suppressing a consumption power and also improving a signal-to-noise ratio by implementing both the zero-point shifting technology and the double sampling technology simultaneously, a delta-sigma modulator includes a first integrator (1), a second integrator (2), a third integrator (3), a local feedback (4), delay units (5), a quantizer (6), a DA converter (7), gains (8a to 8c) of the DA converter, gains (9a to 9c) of the integrators, adders (10), no-delay integrators (11) each having a gain “1”, a gain (12) of the local feedback, a DAC (13) of a gain “1”, a delay unit (5) for delaying output signals of the DA converter (7), and a delay unit (5) for delaying an output signal of the local feedback (4).
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: April 7, 2009
    Assignee: Panasonic Corporation
    Inventors: Tomoaki Maeda, Hisashi Adachi, Taiji Akizuki
  • Patent number: 7466257
    Abstract: The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Publication number: 20080252502
    Abstract: In a delta-sigma modulator circuit, an integrator integrates an input signal, and a quantization circuit quantizes the integrated signal with a predetermined quantization number, and outputs a quantization result signal. A DA converter circuit outputs an analog signal indicating a DA conversion result based on the quantization result signal. An oscillation detector circuit detects that the integrator is in an oscillation state based on the integrated signal, and outputting an oscillation detection signal. A reset circuit resets the integrator based on the oscillation detection signal.
    Type: Application
    Filed: April 9, 2008
    Publication date: October 16, 2008
    Inventors: Tomoaki Maeda, Taiji Akizuki, Hisashi Adachi
  • Publication number: 20080198050
    Abstract: In a delta-sigma modulator including first and second subtractors, first and second integrators, a quantizer, and a DA converter, a first feedback circuit includes first charge holding circuits which hold charges of the analog signal from the DA converter for different sampling intervals, can change a feedback amount of the analog signal from the DA converter, and outputs the analog signal from each first charge holding circuits to the second subtractor. A second feedback circuit includes second charge holding circuits which hold charges of the analog signal from the second integrator for different sampling intervals, can change a feedback amount of the analog signal from the second integrator, and outputs an analog signal from each of the second charge holding circuits to the second subtractor. A controller switches an order of filter characteristic of the delta sigma modulator by changing feedback amounts of the first and second feedback circuits.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 21, 2008
    Inventors: Taiji AKIZUKI, Tomoaki Maeda, Masahiko Sagisaka
  • Publication number: 20080074302
    Abstract: The output of a first integrator is quantized in a quantizer. The quantized signal is subjected to D/A conversion, successively output to a plurality of output paths by a first switching circuit, sampled and held by a plurality of charge-holding circuits of a first feedback circuit, and successively output by a second switching circuit to one of the input terminals of a subtractor. On the other hand, the output signal of the first integrator is successively output by a third switching circuit to a plurality of output paths, sampled and held by a plurality of charge-holding circuits of a second feedback circuit, and successively input to the other input terminal of the subtractor by a fourth switching circuit along with signals held in an input portion, which samples and holds input analog signals. By doing so, a plurality of signals with different sampling timings are integrated accumulatively by the subtractor and the first integrator.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 27, 2008
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Publication number: 20080068246
    Abstract: An A/D converter includes a first switched capacitor block that charges and holds charges by connecting each of a first group of capacitors to a single basic reference voltage at a first timing, and discharges each of the charges held by the first group of capacitors at a second timing, a second switched capacitor block that charges and holds each of the charges discharged by the first group of capacitors respectively in the second group of capacitors at the second timing, and converts each of the charges held by the second group of capacitors to a voltage and outputs the voltages at the first timing, and a quantizer that quantizes an analog input signal using the plurality of voltages output from the second switched capacitor block as reference voltages for each level. A plurality of reference voltages is generated from a single basic reference voltage, based on different amounts of charges held in the plurality of capacitors.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 20, 2008
    Inventors: Taiji Akizuki, Tomoaki Maeda, Hisashi Adachi
  • Publication number: 20080062024
    Abstract: To provide a method of controlling a delta-sigma modulator and a delta-sigma modulator capable of suppressing a consumption power and also improving a signal-to-noise ratio by implementing both the zero-point shifting technology and the double sampling technology simultaneously, a delta-sigma modulator includes a first integrator (1), a second integrator (2), a third integrator (3), a local feedback (4), delay units (5), a quantizer (6), a DA converter (7), gains (8a to 8c) of the DA converter, gains (9a to 9c) of the integrators, adders (10), no-delay integrators (11) each having a gain “1”, a gain (12) of the local feedback, a DAC (13) of a gain “1”, a delay unit (5) for delaying output signals of the DA converter (7), and a delay unit (5) for delaying an output signal of the local feedback (4).
    Type: Application
    Filed: September 6, 2007
    Publication date: March 13, 2008
    Inventors: Tomoaki Maeda, Hisashi Adachi, Taiji Akizuki
  • Publication number: 20060192621
    Abstract: A two-system PLL frequency synthesizer includes, a first PLL frequency synthesizer connected with a power line, a current amount controller having a first constant current source connected between the first PLL frequency synthesizer and a ground line, and a constant current source controller for controlling the current of the first constant current source so as to change it gradually, and a series-connected circuit of a second PLL frequency synthesizer and a second constant current source, connected between the power line and the ground line.
    Type: Application
    Filed: February 24, 2006
    Publication date: August 31, 2006
    Inventors: Tomoaki Maeda, Atsushi Ohara, Koichi Mizuno