Abstract: A semiconductor device of an embodiment includes N-wells and P-wells extending in a first direction and alternately arranged in a second direction orthogonal to the first direction; and a dummy gate formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, in which the dummy gate is formed in a region other than an end portion in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface facing the first surface, and an outline, and an impurity region located on a side of the first surface in the semiconductor substrate. The second surface has a plurality of concave portions, and each of the plurality of concave portions open toward a side opposite to the first surface and extend along a direction perpendicular to a direction in which the semiconductor substrate is susceptible to warping most.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide layer of a first conductive type including a defect region in which a crystal defect exists; a plurality of well regions of a second conductive type formed on the silicon carbide layer; source regions of the first conductive type formed in the well regions; gate oxide films formed on the silicon carbide layer, the well regions and the source regions; gate electrodes formed on the gate oxide films; and a source electrode electrically connected to the well regions and the source regions, wherein the source region is not formed in the defect region.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide layer of a first conductive type including a defect region in which a crystal defect exists; a plurality of well regions of a second conductive type formed on the silicon carbide layer; source regions of the first conductive type formed in the well regions; gate oxide films formed on the silicon carbide layer, the well regions and the source regions; gate electrodes formed on the gate oxide films; and a source electrode electrically connected to the well regions and the source regions, wherein the source region is not formed in the defect region.

Abstract: Provided is a microbicide-containing aqueous composition having a superior effect of stabilizing 5-chloro-2-methyl-4-isothiazolin-3-one. This microbicide composition includes: (A) 5-chloro-2-methyl-4-isothiazolin-3-one; (B) 2,2,6,6-tetramethylpiperidin-1-oxyl; and (C) at least one solvent selected from the group consisting of water and a hydrophilic organic solvent.

Abstract: The object of a silicon carbide semiconductor device according to the present disclosure is to prevent fluctuations in threshold voltage and prevent cracks in a barrier metal. A silicon carbide semiconductor device includes: a silicon carbide substrate; a semiconductor layer formed on the silicon carbide substrate; a gate electrode facing the semiconductor layer through a gate insulating film; an interlayer insulating film covering the gate electrode; a barrier metal formed on the interlayer insulating film; and a top electrode covering the barrier metal, wherein the barrier metal has a two-layer structure of a barrier metal and a barrier metal, and the barrier metal closer to the interlayer insulating film is made of a same metallic material as the barrier metal, the barrier metal being thinner than the barrier metal.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide layer of a first conductive type including a defect region in which a crystal defect exists; a plurality of well regions of a second conductive type formed on the silicon carbide layer; source regions of the first conductive type formed in the well regions; gate oxide films formed on the silicon carbide layer, the well regions and the source regions; gate electrodes formed on the gate oxide films; and a source electrode electrically connected to the well regions and the source regions, wherein the source region is not formed in the defect region.

Abstract: A target CPU executes a user program in synchronism with an asynchronous operation clock signal at higher speed than an operation clock signal of a debugging object system. A control unit portion outputs address bus information, data bus information, and machine cycle information in operation. A POD portion generates various control signals of the debugging object system based on the machine cycle information and then the address bus information, the data bus information, and the machine cycle information to the debugging object system in synchronism with an operation clock signal of the debugging object system. Collection, output, or process of debugging information can thus be executed by use of difference in execution times of the user program between the debugging object system and the target CPU, without halting the debugging object system.