Patents by Inventor Tomoaki Shibata

Tomoaki Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240018306
    Abstract: A resin composition that contains (A) at least one of a polyimide precursor, which is at least one resin selected from the group consisting of a polyamide acid, a polyamide acid ester, a polyamide acid salt, and a polyamide acid amide, or a polyimide resin, and (B) a solvent, and that is used for preparing an insulating film for at least one of a first organic insulating film or a second organic insulating film in a method for producing a semiconductor device including processes (1) to (5).
    Type: Application
    Filed: September 28, 2021
    Publication date: January 18, 2024
    Inventors: Satoshi YONEDA, Yutaka NAMATAME, Tomoaki SHIBATA, Kaori KOBAYASHI, Hitoshi ONOZEKI, Naoya SUZUKI, Toshihisa NONAKA
  • Publication number: 20230268195
    Abstract: A method for manufacturing an electronic component device including: preparing a wiring structure having a wiring portion including a metal wiring and an insulating layer and having two main surfaces opposite to each other, and a connection portion provided on one of the main surfaces of the wiring portion; fixing one or more conductor pins on the wiring substrate in a state in which the one or more conductor pins stand against the connection portion; mounting one or more electronic components on the wiring structure; and forming an encapsulation layer for encapsulating the electronic component and the conductor pin on the wiring structure.
    Type: Application
    Filed: August 31, 2021
    Publication date: August 24, 2023
    Inventors: Tomoaki SHIBATA, Naoya SUZUKI
  • Publication number: 20220246488
    Abstract: Disclosed is a method for manufacturing an electronic component device, including: preparing a sealing structure including a sealing layer having two opposing main surfaces, an electronic component, and a connection portion, the connection portion being exposed on a circuit surface that is one main surface of the sealing layer; preparing a rewiring structure including a rewiring portion having two opposing main surfaces, and a plurality of bumps; and bonding the sealing structure and the rewiring structure in a direction that the circuit surface and the plurality of bumps face each other, with an insulating adhesive layer intervening, and thereby connecting the sealing structure and the rewiring structure.
    Type: Application
    Filed: May 21, 2020
    Publication date: August 4, 2022
    Inventors: Tomoaki SHIBATA, Tsuyoshi OGAWA, Xinrong LI
  • Publication number: 20220246597
    Abstract: Disclosed is a method for manufacturing an electronic component device, including: preparing a sealing structure having a sealing layer having two opposing main surfaces, an electronic component, and a connection portion, the connection portion being exposed on a circuit surface that is one main surface of the sealing layer; preparing a rewiring structure having a rewiring portion having two opposing main surfaces, and a plurality of bumps; and bonding the sealing structure and the rewiring structure in a direction that the circuit surface and the plurality of bumps face each other, with an insulating layer intervening.
    Type: Application
    Filed: May 21, 2020
    Publication date: August 4, 2022
    Inventors: Tomoaki SHIBATA, Tsuyoshi OGAWA, Satoshi YONEDA, Xinrong LI
  • Publication number: 20220157741
    Abstract: Disclosed is a method for producing an electronic component, the method including: disposing a plurality of electronic components on an adhesive layer of a composite substrate including a support, a temporary fixing material layer, and the adhesive layer with a connection part in contact with the adhesive layer interposed between the adhesive layer and the electronic components; fixing the plurality of electronic components to the composite substrate by curing the adhesive layer; forming a sealing layer sealing the electronic components; obtaining a sealed structure by peeling off the temporary fixing material layer from the adhesive layer; and a forming a circuit surface by grinding the sealed structure from the adhesive layer side. The plurality of electronic components include an IC chip and a chip-type passive component.
    Type: Application
    Filed: March 5, 2020
    Publication date: May 19, 2022
    Inventors: Tomoaki SHIBATA, Tsuyoshi OGAWA, Xinrong LI
  • Publication number: 20220148914
    Abstract: Disclosed is a method for manufacturing an electronic component including: forming a via hole extending in a thickness direction of a curable sealing resin layer provided on a base material by an imprint method of pressing a mold into the sealing resin layer from a side opposite to the base material; curing the sealing resin layer; filling the via hole with a conductor precursor; and forming a conductive via by heating the conductor precursor filled in the via hole.
    Type: Application
    Filed: March 5, 2020
    Publication date: May 12, 2022
    Inventors: Tomoaki SHIBATA, Tsuyoshi OGAWA, Xinrong LI
  • Patent number: 11330721
    Abstract: A resin film includes a resin composition for forming a flexible resin layer. The resin composition includes an elastomer, a polymerizable compound, and a polymerization initiator. A laminated film includes a base material film, a resin film formed on the base material film, and a protective film attached to the resin film.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: May 10, 2022
    Assignee: SHOWA DENKO MATERIALS CO., LTD
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Patent number: 11147166
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 12, 2021
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Publication number: 20200253059
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Tomoaki SHIBATA, Hanako YORI, Tomonori MINEGISHI, Hidenori ABE, Takashi MASUKO, Shunsuke OTAKE
  • Patent number: 10674612
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 2, 2020
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Tomoaki Shibata, Hanako Yori, Tomonori Minegishi, Hidenori Abe, Takashi Masuko, Shunsuke Otake
  • Publication number: 20190241694
    Abstract: Disclosed is a curable composition for forming a stretchable resin layer, containing: (A) an elastomer having a polystyrene chain; (B) monofunctional straight-chain alkyl (meth)acrylate; (C) monofunctional (meth)acrylate having an alicyclic group; (D) a difunctional or higher compound having two or more ethylenically unsaturated groups; and (E) a polymerization initiator.
    Type: Application
    Filed: October 25, 2017
    Publication date: August 8, 2019
    Applicant: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Tomoaki SHIBATA, Satoshi UEHARA, Aya IKEDA, Shunsuke OTAKE, Tomonori MINEGISHI, Kazuyoshi TENDOU
  • Patent number: 10287661
    Abstract: A hot-rolled steel sheet is provided having high strength and excellent toughness and ductility includes a composition that contains, on a mass percent basis, 0.04% or more and 0.15% or less of C, 0.01% or more and 0.55% or less of Si, 1.0% or more and 3.0% or less of Mn, 0.03% or less P, 0.01% or less S, 0.003% or more and 0.1% or less of Al, 0.006% or less N, 0.035% or more and 0.1% or less Nb, 0.001% or more and 0.1% or less of V, 0.001% or more and 0.1% or less Ti, and the balance being Fe and incidental impurities, in which the hot-rolled steel sheet includes a microstructure in which the proportion of precipitated Nb to the total amount of Nb is 35% or more and 80% or less, the volume fraction of tempered martensite and/or tempered bainite having a lath interval of 0.2 ?m or more and 1.6 ?m or less is 95% or more at a position 1.0 mm from a surface of the sheet in the thickness direction, and the volume fraction of ferrite having a lath interval of 0.2 ?m or more and 1.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 14, 2019
    Assignee: JFE STEEL CORPORATION
    Inventors: Tomoaki Shibata, Sota Goto
  • Patent number: 10273554
    Abstract: A hot-rolled steel sheet has a chemical composition containing, by mass %, C: 0.030% or more and 0.120% or less, Si: 0.05% or more and 0.50% or less, Mn: 1.00% or more and 2.20% or less, P: 0.025% or less, S: 0.0050% or less, N: 0.0060% or less, Al: 0.005% or more and 0.100% or less, Nb: 0.020% or more and 0.100% or less, Mo: 0.05% or more and 0.50% or less, Ti: 0.001% or more and 0.100% or less, Cr: 0.05% or more and 0.50% or less, Ca: 0.0005% or more and 0.0050% or less, and the balance being Fe and inevitable impurities, and has a microstructure including bainitic ferrite as a main phase and martensite and retained austenite as second phases, wherein a volume fraction of the main phase is 90% or more, an average grain diameter of the main phase is 10 ?m or less, a volume fraction of the martensite is 0.5% or more and 9.5% or less, and a volume fraction of the retained austenite is 0.5% or more and 9.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 30, 2019
    Assignee: JFE Steel Corporation
    Inventors: Tomoaki Shibata, Sota Goto
  • Publication number: 20180288882
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventors: Tomoaki SHIBATA, Hanako YORI, Tomonori MINEGISHI, Hidenori ABE, Takashi MASUKO, Shunsuke OTAKE
  • Publication number: 20170325336
    Abstract: Disclosed is a method for producing a semiconductor device including a circuit board having a flexible resin layer that encapsulates a circuit component. The method may include a step of immersing a flexible substrate in an encapsulant, drying the encapsulant, and thereby encapsulating the circuit component with the encapsulant; and a step of curing the encapsulant, and thereby forming a flexible resin layer.
    Type: Application
    Filed: November 16, 2015
    Publication date: November 9, 2017
    Inventors: Tomoaki SHIBATA, Hanako YORI, Tomonori MINEGISHI, Hidenori ABE, Takashi MASUKO, Shunsuke OTAKE
  • Patent number: 9661159
    Abstract: An information processing device may display a first image indicating a storage area. The information processing device may display a second image in response to receiving a first specific operation performed on the first image. The information processing device may receive a second specific operation for selecting the second image. The information processing device may receive first path information in response to receiving the second specific operation The first path information may indicate a location of the storage area. The information processing device may send the first execution instruction to the image processing device, in the case that the second specific operation is received. The information processing device may receive scan data from the image processing device. The information processing device may store a data file of the received scan data in the storage area designated by the first path information.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: May 23, 2017
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Tomoki Nakamura, Yusaku Takahashi, Tomoaki Shibata, Junjiro Yoshida
  • Patent number: D839348
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 29, 2019
    Assignee: PENTEL KABUSHIKI KAISHA
    Inventors: Hidekazu Nakazawa, Tomoaki Shibata
  • Patent number: D865869
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: November 5, 2019
    Assignee: PENTEL KABUSHIKI KAISHA
    Inventor: Tomoaki Shibata
  • Patent number: D876540
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: February 25, 2020
    Assignee: PENTEL KABUSHIKI KAISHA
    Inventor: Tomoaki Shibata
  • Patent number: D902312
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 17, 2020
    Assignee: Pentel Kabushiki Kaisha
    Inventor: Tomoaki Shibata