Patents by Inventor Tomoaki Tajiri

Tomoaki Tajiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090311862
    Abstract: By removing residual mechanical stress generated during processing, wafers can be manufactured while suppressing deformation and cracking of the wafer even if the wafer is a large-diameter wafer. A method for manufacturing a wafer, includes: a slicing step (S10) for slicing an ingot to obtain a wafer; a double-sided simultaneous grinding step (S20) for roughly grinding the cut surfaces of each wafer; a chamfering step (S22) for chamfering the edge portion of the wafer; a double-sided simultaneous processing step for simultaneously processing both faces of the wafer so as to remove residual mechanical stress generated on the both faces thereof due to the slicing step and the double-sided grinding step; a single-sided finishing step for separately performing finishing processing on at least one face of the wafer; and a cleaning step for cleaning the wafer.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 17, 2009
    Applicant: SUMCO TECHXIV CORPORATION
    Inventors: Tomoaki Tajiri, Daisuke Maruoka
  • Publication number: 20090156101
    Abstract: A polishing apparatus comprises a polishing plate (24), an abrasive cloth (25) attached to the surface of the polishing plate (24), a chuck (19) for holding and pressing one surface of a wafer (39) against the abrasive cloth (25), and a circular retaining ring (23) concentrically arranged on the periphery of the chuck (19). The retaining ring (23) is rotatable and vertically movable with respect to the chuck (19), and is pressed against the abrasive cloth (25) during the lapping step. The retaining ring (23) is lifted upward during the final polishing step, thereby preventing lapping grains from being brought into the final polishing stage. Accordingly, lapping and final polishing can be successively conducted using the same polishing head. With this structure, cost cutting of the apparatus can be realized, since lapping and final polishing are successively conducted using the same polishing head without bringing the lapping grains used for lapping into the final polishing stage.
    Type: Application
    Filed: February 13, 2009
    Publication date: June 18, 2009
    Applicant: KOMATSU DENSHI KINZOKU KABUSHIKI KAISHA
    Inventors: Masamitsu Kitahashi, Toshiyuki Kamei, Hidetoshi Takeda, Hiroyuki Tokunaga, Tomoaki Tajiri
  • Publication number: 20060057942
    Abstract: A polishing apparatus comprises a polishing plate (24), an abrasive cloth (25) attached to the surface of the polishing plate (24), a chuck (19) for holding and pressing one surface of a wafer (39) against the abrasive cloth (25), and a circular retaining ring (23) concentrically arranged on the periphery of the chuck (19). The retaining ring (23) is rotatable and vertically movable with respect to the chuck (19), and is pressed against the abrasive cloth (25) during the lapping step. The retaining ring (23) is lifted upward during the final polishing step, thereby preventing lapping grains from being brought into the final polishing stage. Accordingly, lapping and final polishing can be successively conducted using the same polishing head. With this structure, cost cutting of the apparatus can be realized, since lapping and final polishing are successively conducted using the same polishing head without bringing the lapping grains used for lapping into the final polishing stage.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 16, 2006
    Applicant: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Masamitsu Kitahashi, Toshiyuki Kamei, Hidetoshi Takeda, Hiroyuki Tokunaga, Tomoaki Tajiri
  • Patent number: 5851924
    Abstract: A method for fabricating a semiconductor wafer to reduce the number of processing steps and produce low-cost wafers in a short time is disclosed. The method involves surface grinding both the front surface and back surface of a single-crystal silicon wafer which has been sliced from a rod and chamfered. In the surface grinding step, the size numbers of abrasive grains are larger than #2000 for front surface grinding, and smaller than #600 for back surface grinding. The front surface is then chemical polished as a mirror surface which satisfies the requirement of a later photolithography step. Moreover, a deformation layer formed on the back surface of the semiconductor wafer is partially etched and left to provide an extrinsic gettering function. An epitaxial layer can be formed on the front surface to make the wafer an epitaxial wafer. The method of the present invention requires fewer process steps as compared with conventional methods, thereby reducing manufacturing time and cost.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: December 22, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Atsuo Nakazawa, Yuuichirou Mukai, Tomoaki Tajiri