Patents by Inventor Tomoaki Ushiro

Tomoaki Ushiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5850682
    Abstract: In a chip type common mode choke coil, a plurality of non-magnetic sheets on which conductor lines are formed are laminated one on another to form a non-magnetic member, and the conductor lines are connected to form primary and secondary coils inside the non-magnetic member, and a pair of magnetic layers are formed on the upper and lower surface of the non-magnetic member, and magnetic cores are arranged substantially at the centers of the loops of the coils in such a manner that they penetrate the non-magnetic member and are connected to the pair of magnetic layers, whereby a closed magnetic path crossing the primary and secondary coils is formed.
    Type: Grant
    Filed: July 9, 1996
    Date of Patent: December 22, 1998
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoaki Ushiro
  • Patent number: 5753176
    Abstract: A process for producing a voltage-dependent nonlinear resistor that contains zinc oxide as a major component and that also contains a minor oxide component, is improved by the steps of adding an organometallic compound as the minor oxide component to the powder of zinc oxide, mixing the two components, forming the mixture into a shape and sintering the shape. The organometallic compound as the minor oxide component is either a compound in which a hydrocarbon group is bound to a metal atom or a compound in which the hydrogen atom in a carboxyl, hydroxyl, imino group, etc., is replaced by a metal. The method is capable of reducing the scattering of the electrical characteristics of the voltage-dependent nonlinear resistor, which contributes to an improvement of the change of varistor voltage by surge current.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: May 19, 1998
    Assignee: Murata Manufacturing Co. Ltd.
    Inventors: Tomoaki Ushiro, Hiroshi Komatsu, Tooru Tominaga, Hiroyuki Kubota, Kazutaka Nakamura, Masahiro Yuruki
  • Patent number: 5655287
    Abstract: Two parts of magnetic layers are placed so as to clamp a coil forming unit consisting of an alternated laminate of non-magnetic layers and electrode layers. The coil forming unit is surrounded by the magnetic body to form a closed magnetic circuit. When manufacturing the laminated transformer, a plurality of sets of U-shaped electrodes are deposited on non-magnetic green sheets. Then, the non-magnetic green sheets are laminated to form the coil forming unit consisting of the alternated laminate of the non-magnetic layers and the electrode layers. Magnetic green sheets are laminated thereto and clamp the non-magnetic green sheets therebetween to form a laminate. The laminate is pressed and additional magnetic body portions are formed in the center and on the side faces of the coil forming units. The laminate is pressed and cut into green elements. The green elements are sintered into monolithic bodies of the laminated transformer.
    Type: Grant
    Filed: September 20, 1995
    Date of Patent: August 12, 1997
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoaki Ushiro
  • Patent number: 5551146
    Abstract: In A method of manufacturing a solid inductor having an inner conductor formed by passing through a magnetic, material. A vitreous diffused material is applied to the surface of the magnetic material, and the diffused material is diffused into the magnetic material by heat treatment, to form a diffusion layer exhibiting low permeability. The thickness of this diffusion layer is adjusted, thereby to make it possible to adjust the inductance value of the solid inductor as well as to improve resistance to humidity of the solid inductor.
    Type: Grant
    Filed: August 10, 1994
    Date of Patent: September 3, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshio Kawabata, Hiroyuki Takeuchi, Hisashi Katsurada, Kazutaka Nakamura, Tomoaki Ushiro
  • Patent number: 5552756
    Abstract: In a chip type common mode choke coil, a plurality of non-magnetic sheets on which conductor lines are formed are laminated one on another to form a non-magnetic member, and the conductor lines are connected to form primary and secondary coils inside the non-magnetic member, and a pair of magnetic layers are formed on the upper and lower surface of the non-magnetic member, and magnetic cores are arranged substantially at the centers of the loops of the coils in such a manner that they penetrate the non-magnetic member and are connected to the pair of magnetic layers, whereby a closed magnetic path crossing the primary and secondary coils is formed.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: September 3, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomoaki Ushiro
  • Patent number: 5453316
    Abstract: A composite electronic part includes a dielectric ceramic portion consisting of a Pb group dielectric material. Inside the dielectric ceramic portion, an internal electrode constituting a portion of a capacitor is formed. The dielectric ceramic portion is bonded to a magnetic ceramic portion consisting of a Ni--Zn group ferrite material by an intermediate layer consisting of a ceramic material containing Pb, Ni, Fe and Nb as main components. Inside the magnetic ceramic portion, an internal electrode constituting a portion of an inductor is formed. Furthermore, at end portions of the dielectric ceramic portion, intermediate layer and magnetic ceramic portion, a plurality of external electrodes consisting of, for example, Ag are formed, and connected to the predetermined internal electrodes.
    Type: Grant
    Filed: May 10, 1994
    Date of Patent: September 26, 1995
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Hiroshi Morii, Hiroshi Komatsu, Tomoaki Ushiro, Tomio Yamasaki, Toshio Kawabata
  • Patent number: 5430429
    Abstract: A resistor 1 in which at least one resistance film 4 is embedded in a ceramic sintered body 3, glass is diffused into the sintered body 3 to form a glass diffusion layer 6, and both end faces 4a and 4b of the resistance film 4 are respectively exposed to both end faces 3a and 3b of the ceramic sintered body 3.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: July 4, 1995
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kazutaka Nakamura, Hiroyuki Kubota, Yasunobu Yoneda, Akinori Nakayama, Tohru Tominaga, Tomoaki Ushiro
  • Patent number: 5359311
    Abstract: In a solid inductor having an inner conductor formed by passing through a magnetic material, a vitreous diffused material is applied to the surface of the magnetic material, and the diffused material is diffused into the magnetic material by heat treatment, to form a diffusion layer exhibiting low permeability. The thickness of this diffusion layer is adjusted, thereby to make it possible to adjust the inductance value of the solid inductor as well as to improve resistance to humidity of the solid inductor.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: October 25, 1994
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toshio Kawabata, Hiroyuki Takeuchi, Hisashi Katsurada, Kazutaka Nakamura, Tomoaki Ushiro
  • Patent number: 5324986
    Abstract: A chip type varistor in which first and second inner electrodes are embedded in a sintered body obtained by laminating a plurality of semiconductor ceramics layers so as not to be overlapped with each other in the direction of thickness of the ceramics layers, respective one edges of the first and second inner electrodes are led out to one and the other of a pair of side surfaces opposed to each other of the sintered body and are electrically connected to outer electrodes formed on the pair of side surfaces of the sintered body, respectively, a non-connected type inner electrode which is not electrically connected to the above described outer electrodes is embedded in the sintered body, and the non-connected type inner electrode is arranged so as to be overlapped with the first and second inner electrodes while being separated by the semiconductor ceramics layer.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: June 28, 1994
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasushi Ueno, Akinori Nakayama, Kazutaka Nakamura, Yasunobu Yoneda, Yukio Sakabe, Tomoaki Ushiro
  • Patent number: 5250923
    Abstract: A conductor pattern for forming coils and lead-out electrodes which are led out from the coils are formed on a magnetic substance sheet. Furthermore, said magnetic substance sheet is provided with through-holes for connecting the conductor patterns. The magnetic substance sheets disposed respectively just over and just under the conductor pattern that becomes the lead-out electrodes are coated with non-magnetic material paste. A laminated chip common mode choke coil is produced by laminating these magnetic substance sheets and baking them integrally and thereafter forming external electrodes. The non-magnetic material diffuses into the magnetic substance sheet by baking the lamination of the magnetic substance sheets, and the permeability of that portion becomes low. Therefore, the magnetic reluctance around the lead-out electrode becomes high, thus reducing leakage flux around that portion. Thereby, coupling between two coils formed in the choke coil becomes good.
    Type: Grant
    Filed: December 28, 1992
    Date of Patent: October 5, 1993
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tomoaki Ushiro, Toshio Kawabata, Daiji Kono, Hisato Oshima
  • Patent number: 4920915
    Abstract: A work holder (12) for holding a workpiece (2) while partially masking the same by use of a mask (18). The workpiece and the mask are elastically pressed against each other by an aggregate (15) of heat-resistant fiber such as metal fiber or ceramic fiber, so that the workpiece and the mask are brought into close contact with each other. This work holder is adapted to form a resistor film (9) on a part of the surface of a chip (2) to form a chip-type resistor (1), for example, by a thin film forming method such as sputtering.
    Type: Grant
    Filed: June 5, 1989
    Date of Patent: May 1, 1990
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsuo Senda, Toshi Numata, Tomoaki Ushiro, Takuji Nakagawa, Masaaki Taniguchi