Abstract: A semiconductor device according to embodiments includes: a first semiconductor layer having a first source region, a first drain region, and a first channel region; a second semiconductor layer having a second source region, a second drain region, and a second channel region; and a gate electrode that is formed to cover the first channel region and the second channel region with a gate insulating film interposed. The semiconductor device includes a first CMOS circuit and a second CMOS circuit each formed of the combination of a first conductive type MOS having the first semiconductor layer and a second conductive type MOS having the second semiconductor layer. The first semiconductor layer is stacked in a (2n?1)th layer. The second semiconductor layer is stacked in a 2nth layer (1?n?N, N?2, and n and N are integers).

Abstract: A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Abstract: A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Abstract: A semiconductor memory device of an embodiment includes memory cells 2, a write-back determining unit 7, and a read controller 8. Each memory cell 2 is capable of writing and reading through different paths. The write-back determining unit 7 determines whether or not to perform the write-back for a non-selected column, at the time of the write for a selected column. On the basis of the determination result of the write-back determining unit 7, the read controller 8 controls the read of the data used in the write-back for the non-selected column.

Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

Abstract: This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

Abstract: A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

Abstract: A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.

Abstract: A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

Abstract: A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

Abstract: This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

Abstract: A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.