Patents by Inventor Tomoe Nishimura
Tomoe Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12700468Abstract: According to one embodiment, a magnetic memory includes: a magnet configured to store data and shift the data from a first area to a second area by domain wall movement caused by a shift operation; an interconnect spaced apart from the magnet and configured to apply a write field to the magnet at a time of a write operation; and a control circuit configured to cause a shift current for shifting the data to flow in the magnet and to cause a write current for generating the write field to flow in the interconnect, wherein the write current includes a first pulse supplied to the interconnect and a second pulse supplied to the interconnect after the first pulse, and a pulse width of the second pulse is smaller than a pulse width of the first pulse.Type: GrantFiled: September 10, 2024Date of Patent: August 4, 2026Assignee: Kioxia CorporationInventors: Michael Arnaud Quinsat, Naoharu Shimomura, Yoshihiro Ueda, Tsuyoshi Kondo, Nobuyuki Umetsu, Susumu Hashimoto, Jun Iwata, Tomoe Nishimura, Masaki Kado, Tsutomu Nakanishi, Yasuaki Ootera
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Patent number: 12694917Abstract: According to one embodiment, a magnetic memory includes first magnetic members extending in a first direction, first wirings extending in a second direction and spaced from each other in a third direction, and a second magnetic member. The second magnetic member has a first portion above the first wirings, a second portion extending in the second direction between adjacent first wirings, a third portion below the plurality of first wirings, and a fourth portion with a part inside an upper end portion of a first magnetic member. A third wiring extends in the third direction and is connected to lower end portions of first magnetic members.Type: GrantFiled: September 5, 2023Date of Patent: July 28, 2026Assignee: Kioxia CorporationInventors: Yasuaki Ootera, Tsutomu Nakanishi, Nobuyuki Umetsu, Tomoe Nishimura, Susumu Hashimoto, Masaki Kado, Tsuyoshi Kondo
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Publication number: 20250246254Abstract: According to one embodiment, a magnetic memory includes: a magnet configured to store data and shift the data from a first area to a second area by domain wall movement caused by a shift operation; an interconnect spaced apart from the magnet and configured to apply a write field to the magnet at a time of a write operation; and a control circuit configured to cause a shift current for shifting the data to flow in the magnet and to cause a write current for generating the write field to flow in the interconnect, wherein the write current includes a first pulse supplied to the interconnect and a second pulse supplied to the interconnect after the first pulse, and a pulse width of the second pulse is smaller than a pulse width of the first pulse.Type: ApplicationFiled: September 10, 2024Publication date: July 31, 2025Applicant: Kioxia CorporationInventors: Michael Arnaud Quinsat, Naoharu Shimomura, Yoshihiro Ueda, Tsuyoshi Kondo, Nobuyuki Umetsu, Susumu Hashimoto, Jun Iwata, Tomoe Nishimura, Masaki Kado, Tsutomu Nakanishi, Yasuaki Ootera
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Publication number: 20240221809Abstract: According to one embodiment, a magnetic memory includes first magnetic members extending in a first direction, first wirings extending in a second direction and spaced from each other in a third direction, and a second magnetic member. The second magnetic member has a first portion above the first wirings, a second portion extending in the second direction between adjacent first wirings, a third portion below the plurality of first wirings, and a fourth portion with a part inside an upper end portion of a first magnetic member. A third wiring extends in the third direction and is connected to lower end portions of first magnetic members.Type: ApplicationFiled: September 5, 2023Publication date: July 4, 2024Inventors: Yasuaki OOTERA, Tsutomu NAKANISHI, Nobuyuki UMETSU, Tomoe NISHIMURA, Susumu HASHIMOTO, Masaki KADO, Tsuyoshi KONDO
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Patent number: 7245568Abstract: A disc recording and reproducing device disclosed herein comprises: a resuming section which resumes writing of record data; a first reproduction synchronization signal output section which reproduces the record data recorded on a recorded data region, sequentially extracts a synchronization signal from the reproduced record data, and outputs a first reproduction synchronization signal; a reliability judging section which only detects a frame having a period in accordance with a predetermined standard from the first reproduction synchronization signal, and outputs the frame as a reliability synchronization signal; a synchronization signal phase retaining section which outputs a retained phase signal that retains a phase of the frame of the reliability synchronization signal; a second reproduction synchronization signal output section which reproduces the record data recorded on an additional data region, sequentially extracts the synchronization signal, and outputs a second reproduction synchronization signalType: GrantFiled: October 7, 2003Date of Patent: July 17, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Akira Hikimura, Kunihiko Kodama, Tomoe Nishimura
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Patent number: 6795385Abstract: An optical disk recording and reproducing apparatus comprise, a buffer circuit which receive and store data and output the stored data, an EFM modulation circuit which receive data output from the buffer circuit, adding a frame synchronous signal and sub-code data, subjecting these items of data to the EFM modulation to create record data, a buffer remaining amount control circuit for detecting the remaining amount of data stored in the buffer circuit, a record control circuit for conducting the control for temporarily suspending the recording operation to the optical disk at an arbitrary position of the main data of the record data excluding the frame synchronous signal and the sub-code data in the case where the detection result of the remaining amount of data in the buffer remaining amount control circuit corresponds to the state in which the buffer underrun is generated.Type: GrantFiled: August 16, 2001Date of Patent: September 21, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Tomoe Nishimura, Akira Hikimura, Kunihiko Kodama, Katsutoshi Moriyama
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Publication number: 20040179444Abstract: A disc recording and reproducing device disclosed herein comprises: a resuming section which resumes writing of record data; a first reproduction synchronization signal output section which reproduces the record data recorded on a recorded data region, sequentially extracts a synchronization signal from the reproduced record data, and outputs a first reproduction synchronization signal; a reliability judging section which only detects a frame having a period in accordance with a predetermined standard from the first reproduction synchronization signal, and outputs the frame as a reliability synchronization signal; a synchronization signal phase retaining section which outputs a retained phase signal that retains a phase of the frame of the reliability synchronization signal; a second reproduction synchronization signal output section which reproduces the record data recorded on an additional data region, sequentially extracts the synchronization signal, and outputs a second reproduction synchronization signalType: ApplicationFiled: October 7, 2003Publication date: September 16, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Akira Hikimura, Kunihiko Kodama, Tomoe Nishimura
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Publication number: 20020024901Abstract: An optical disk recording and reproducing apparatus comprise, a buffer circuit which receive and store data and output the stored data, an EFM modulation circuit which receive data output from the buffer circuit, adding a frame synchronous signal and sub-code data, subjecting these items of data to the EFM modulation to create record data, a buffer remaining amount control circuit for detecting the remaining amount of data stored in the buffer circuit, a record control circuit for conducting the control for temporarily suspending the recording operation to the optical disk at an arbitrary position of the main data of the record data excluding the frame synchronous signal and the sub-code data in the case where the detection result of the remaining amount of data in the buffer remaining amount control circuit corresponds to the state in which the buffer underrun is generated.Type: ApplicationFiled: August 16, 2001Publication date: February 28, 2002Inventors: Tomoe Nishimura, Akira Hikimura, Kunihiko Kodama, Katsutoshi Moriyama