Abstract: An SRAM comprises a memory cell array composed of a number of SRAM cells arranged in the form of a matrix, and a memory reading circuit including a sense amplifier for differentially amplifying a potential difference between a pair of complementary bit lines, for reading data from the memory cell array. The memory reading circuit includes a delay circuit for making the timing of a signal for deactivating a word line activating the SRAM cells on the same line and the timing of a signal for enabling the sense amplifier, consistent with each other. The delay circuit includes a number of cascade-connected inverters, and the number of the cascade-connected inverters can be adjusted by a focused ion beam. Thus, the reduction of the power consumption and the elevation of the reading speed, which are conventionally considered to be factors incompatible with each other, can be simultaneously realized by optimizing the number of the cascade-connected inverters in the delay circuit.