Patents by Inventor Tomofumi Arakawa
Tomofumi Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11056463Abstract: The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.Type: GrantFiled: December 11, 2015Date of Patent: July 6, 2021Assignee: SONY CORPORATIONInventors: Hiroshi Takahashi, Tomofumi Arakawa, Minoru Ishida
-
Publication number: 20170317061Abstract: The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be laminated and the laminated semiconductor apparatuses to be identified. A semiconductor apparatus that is laminated and integrated with a plurality of semiconductor apparatuses, includes a first penetrating electrode for connecting with the other semiconductor apparatuses and a second penetrating electrode that connects the first penetrating electrode and an internal device, the second penetrating electrode being arranged at a position that differs for each of the laminated semiconductor apparatuses. The second penetrating electrode indicates a lamination position at a time of lamination. An address of each of the laminated semiconductor apparatuses in a lamination direction is identified by writing using external signals after lamination. The present technology is applicable to a memory chip and an FPGA chip.Type: ApplicationFiled: December 11, 2015Publication date: November 2, 2017Inventors: Hiroshi TAKAHASHI, Tomofumi ARAKAWA, Minoru ISHIDA
-
Patent number: 7646209Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.Type: GrantFiled: July 10, 2006Date of Patent: January 12, 2010Assignee: Sony CorporationInventors: Mitsuhiro Oomori, Tomofumi Arakawa
-
Patent number: 7483288Abstract: Disclosed is a memory device which can minimize a reduction in area efficiency even when the memory device has a small storage capacity and which can hide the access time to a row line.Type: GrantFiled: February 1, 2002Date of Patent: January 27, 2009Assignee: Sony CorporationInventor: Tomofumi Arakawa
-
Patent number: 7411412Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.Type: GrantFiled: August 7, 2006Date of Patent: August 12, 2008Assignee: Sony CorporationInventors: Tomofumi Arakawa, Mutsuhiro Ohmori
-
Patent number: 7315970Abstract: A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.Type: GrantFiled: March 14, 2005Date of Patent: January 1, 2008Assignee: Sony CorporationInventors: Tomofumi Arakawa, Hiroaki Kodama, Kazutoshi Inoue
-
Publication number: 20070234137Abstract: A semiconductor integrated circuit, able to repair a fault and normally operate as an overall circuit even when a fault occurs in a portion of the circuit, and able to reduce a change of signal delay along with the repair of the fault, including N (larger than 2) number of circuit modules which can replace each other's functions; circuit blocks each including R (larger than 1 but smaller than N) number of I/O units for outputting at least one signal to one circuit module, and receiving at least one signal generated in the one circuit module; and a circuit module selection unit configured to select R number of circuit modules from among the N number of circuit modules in response to a control signal, connect the selected R number of circuit modules and R number of I/O units of the circuit block in a 1:1 correspondence, and connect one circuit module selected from at least two circuit modules in response to the control signal to each of the R number of I/O units, and a method of producing the same.Type: ApplicationFiled: July 10, 2006Publication date: October 4, 2007Applicant: Sony CorporationInventors: Mutsuhiro Oomori, Tomofumi Arakawa
-
Patent number: 7271488Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.Type: GrantFiled: December 21, 2005Date of Patent: September 18, 2007Assignee: Sony CorporationInventors: Tomofumi Arakawa, Mutsuhiro Ohmori
-
Publication number: 20070057690Abstract: A semiconductor integrated circuit including: N modules set in their functions in accordance with input function setting data, a circuit block having R number of I/O parts, and a module selection part for selecting R number of modules from among the N number of modules connecting the selected R number of modules and R number of I/O parts of the circuit block and connecting one module selected from among at least two modules to each of the R number of I/O parts. Each of the R number of I/O parts has a data holding part for holding a function setting data and inputting the held function setting data to the destination module, and N modules are able to replace functions of each other when the input function setting data are the same.Type: ApplicationFiled: August 7, 2006Publication date: March 15, 2007Applicant: Sony CorporationInventors: Tomofumi Arakawa, Mutsuhiro Ohmori
-
Publication number: 20060151883Abstract: A semiconductor integrated circuit having a plurality of interconnect layers and at least one via connecting interconnects of two adjacent interconnect layers, wherein each interconnect layer has a plurality of first interconnect groups and second interconnect groups arranged respectively in a row and a column in a matrix. The first and the second interconnect groups are alternately arranged in each row and in each column of the matrix arranged facing each other between two adjacent interconnect layers. The first and second interconnect groups facing each other between the layers have crossing parts where they can be connected through vias.Type: ApplicationFiled: December 21, 2005Publication date: July 13, 2006Inventors: Tomofumi Arakawa, Mutsuhiro Ohmori
-
Publication number: 20060113567Abstract: A semiconductor integrated circuit able to repair a defect of a circuit cell without greatly changing interconnects, that is, a semiconductor integrated circuit comprising a plurality of circuit cells aligned in a matrix and groups of interconnects connecting at least a part of the plurality of circuit cells other than one or more lines of unused circuit cells aligned in a row direction or a column direction.Type: ApplicationFiled: October 13, 2005Publication date: June 1, 2006Applicant: Sony CorporationInventors: Mutsuhiro Ohmori, Tomofumi Arakawa
-
Publication number: 20050210186Abstract: A semiconductor device able to improve data retaining characteristics and decrease power consumption, further able to realize more unrestricted system without increasing excessive circuits, and having the following: an ALPG receiving a start signal and a mode selection signal to generate commands and addresses with respect to a DRAM circuit with the predetermined patterns in accordance with modes, and outputting an ending signal when ending a pattern generating processing in each of modes; an ECC circuit receiving a start signal and a mode selection signal indicating a parity generation mode to generate a parity based on data read from the DRAM circuit, receiving the start signal and a mode selection signal indicating an error correction mode to perform an error correction with respect to data read from the DRAM circuit based on the parity generated in the parity generation mode and outputting data after correcting; and an interface circuit.Type: ApplicationFiled: March 14, 2005Publication date: September 22, 2005Applicant: Sony CorporationInventors: Tomofumi Arakawa, Hiroaki Kodama, Kazutoshi Inoue
-
Patent number: 6859400Abstract: The present invention provides a semiconductor memory device comprising: a memory cell; a sense amplifier for amplifying data read out from the memory cell; and a first to a third latch circuit connected in parallel with the sense amplifier.Type: GrantFiled: February 3, 2003Date of Patent: February 22, 2005Assignee: Sony CorporationInventor: Tomofumi Arakawa
-
Publication number: 20030179620Abstract: The present invention provides a semiconductor memory device comprising: a memory cell; a sense amplifier for amplifying data read out from the memory cell; and a first to a third latch circuit connected in parallel with the sense amplifier.Type: ApplicationFiled: February 3, 2003Publication date: September 25, 2003Inventor: Tomofumi Arakawa
-
Publication number: 20030002320Abstract: Disclosed is a memory device which can minimize a reduction in area efficiency even when the memory device has a small storage capacity and which can hide the access time to a row line.Type: ApplicationFiled: February 1, 2002Publication date: January 2, 2003Inventor: Tomofumi Arakawa