Abstract: An activation system of a work machine includes a vehicle body control unit outputting a control signal to drive a vehicle body of the work machine with power supplied by a power source, and an authentication unit performing authentication of an operator of the work machine. The activation system of a work machine first activates the authentication unit, and activates the vehicle body control unit when the authentication unit authenticates that the operator boarding the work machine is a specific operator.

Abstract: A work machine start-up system includes a control unit configured to control a work machine, a proximity detection unit configured to detect that a specific operator is in close proximity to the work machine, and a start-up unit configured to start at least part of the control unit when it is detected that the specific operator is in close proximity to the work machine.

Abstract: An authentication unit performs authentication of an operator. A storage unit stores setting data associated with a plurality of operators. A vehicle body control unit outputs a control signal to drive a vehicle body of the work machine with power supplied by a power source, based on the setting data associated with the authenticated operator. The authentication unit receives the authentication when the power source is stopped and does not receive the authentication when the power source is driven.

Abstract: A semiconductor device capable of determining plural transfer speeds with a small-scale circuit, and an information processing system having the semiconductor device are provided. The semiconductor device has a frequency determining circuit that receives a data signal on which plural transfer speeds can be set and that determines a transfer speed of the data signal. The frequency determining circuit latches the data signal at each of plural timings continuing with a predetermined interval, detects how many times a data switching occurs consecutively, based on the latched plural data, and determines the transfer speed of the data signal from the result of the detection.

Abstract: A semiconductor device capable of determining plural transfer speeds with a small-scale circuit, and an information processing system having the semiconductor device are provided. The semiconductor device has a frequency determining circuit that receives a data signal on which plural transfer speeds can be set and that determines a transfer speed of the data signal. The frequency determining circuit latches the data signal at each of plural timings continuing with a predetermined interval, detects how many times a data switching occurs consecutively, based on the latched plural data, and determines the transfer speed of the data signal from the result of the detection.

Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.

Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.

Abstract: A technique capable of determining a frequency of a data signal having a mixture of short and long pulse widths is provided. In a frequency determining circuit for determining a frequency from different data signals having a plurality of frequencies, the frequency determining circuit includes a circuit which acquires the different data signals having the plurality of frequencies and determines the frequency based on the number of counts of the signal having the pulse width shorter than the predetermined pulse width. For example, the signal having the pulse width shorter than the predetermined pulse width is detected, and the number of pulses of the detected signal is counted. By previously making correspondence of the frequency with the number of counts of the pulse, the frequency can be determined based on the number of counts.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: A semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption in a simple configuration is provided. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout.

Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.

Abstract: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout.

Abstract: Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it.

Abstract: A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

Abstract: The present invention provides a dynamic RAM which can be operated at a low voltage and realizes the enhancement of a read margin and an area-saving layout.

Abstract: A semiconductor integrated circuit device capable of achieving higher integration and simplification of manufacturing processes is provided. Circuitry is provided which includes a first N-channel MOSFET and a first p-channel MOSFET each having a gate insulating dielectric film with a first film thickness, wherein a poly-silicon layer making up a gate electrode is doped with an N-type impurity. The circuitry also includes a second N-channel MOSFET having a gate insulator film with a second film thickness thinner than the first thickness, wherein an N-type impurity is doped into a polysilicon layer making up a gate electrode, and a second P-channel MOSFET with a P-type impurity being doped into a polysilicon layer making up a gate electrode. The gate electrodes of the first N-channel MOSFET and first P-channel MOSFET are integrally formed and mutually connected together.