Patents by Inventor Tomofumi SUSAKI

Tomofumi SUSAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825161
    Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.
    Type: Grant
    Filed: March 9, 2014
    Date of Patent: November 21, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Kazuhiko Matsumoto, Kenzo Maehashi, Tomofumi Susaki, Yasuhide Ohno, Kosuke Matsuzaki, Guillaume Hubert Frederic Hackenberger
  • Patent number: 9605357
    Abstract: A method for depositing a magnesium oxide thin film on a substrate by a laser abrasion method using a sintered body or single crystal of magnesium oxide as a target. In this method, a flat processed film made of magnesium oxide having a (111) plane as its front surface is prepared, using a substrate made of strontium titanate having a (111) plane as its principal surface or yttria-stabilized zirconia having a (111) plane as its principal surface, by directly depositing a film on the principal surface of the substrate and epitaxially growing the film.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 28, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Tomofumi Susaki, Hideo Hosono, Tadahiro Fujihashi, Yoshitake Toda
  • Publication number: 20160027908
    Abstract: Provided is a logical operation element that performs logical operations on three or more inputs using a single unique device. The logical operation element 30 is provided with an electrode 5A and the other electrode 5B that are provided to have a nanogap, a metal nanoparticle 7 arranged between the electrode 5A and the other electrode 5B in insulated state, and a plurality of gate electrodes 5C, 5D, 11, 11A, 11B for adjusting a charge of the metal nanoparticle 7. Electric current that flows between the electrode 5A and the other electrode 5B is controlled in accordance with the voltage applied to three or more of the gate electrodes 5C, 5D, 11, 11A, 11B.
    Type: Application
    Filed: March 9, 2014
    Publication date: January 28, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Yutaka Majima, Toshiharu Teranishi, Kazuhiko Matsumoto, Kenzo Maehashi, Tomofumi Susaki, Yasuhide Ohno, Kosuke Matsuzaki, Guillaume Hubert Frederic Hackenberger
  • Publication number: 20140230724
    Abstract: A method for depositing a magnesium oxide thin film on a substrate by a laser abrasion method using a sintered body or single crystal of magnesium oxide as a target. In this method, a flat processed film made of magnesium oxide having a (111) plane as its front surface is prepared, using a substrate made of strontium titanate having a (111) plane as its principal surface or yttria-stabilized zirconia having a (111) plane as its principal surface, by directly depositing a film on the principal surface of the substrate and epitaxially growing the film.
    Type: Application
    Filed: March 9, 2012
    Publication date: August 21, 2014
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Tomofumi Susaki, Hideo Hosono, Tadahiro Fujihashi, Yoshitake Toda
  • Patent number: 8742393
    Abstract: The SrTiO3 buffer layer is formed by lamination of the Sr2+O2? layer and the Ti4+O24? layer. The surface of the buffer layer is terminated with the Ti4+O24? layer. On the buffer layer, a LaAlO3 thin film layer is formed. The thin film layer includes a La3+O2? layer and an Al3+O24? layer alternately laminated in order on the SrTiO3 buffer layer.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Tokyo Institute of Technology
    Inventors: Tomofumi Susaki, Hideo Hosono
  • Publication number: 20130032778
    Abstract: The SrTiO3 buffer layer is formed by lamination of the Sr2+O2? layer and the Ti4+O24? layer. The surface of the buffer layer is terminated with the Ti4+O24? layer. On the buffer layer, a LaAlO3 thin film layer is formed. The thin film layer includes a La3+O2? layer and an Al3+O24? layer alternately laminated in order on the SrTiO3 buffer layer.
    Type: Application
    Filed: March 8, 2012
    Publication date: February 7, 2013
    Applicant: TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Tomofumi SUSAKI, Hideo HOSONO