Patents by Inventor Tomofumi Zushi

Tomofumi Zushi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10685981
    Abstract: A semiconductor memory device according to an embodiment includes a base portion, a laminated body, a second conductive layer, and a columnar body. The columnar body includes a semiconductor body and a charge storage film. The semiconductor body includes a first region and a second region. The first region extends from a connection portion between the semiconductor body and the first semiconductor portion to the inside of the second conductive layer. The first region includes a first material. The second region is positioned closer to the laminated body than the first region is and is configured such that at least a portion is present within the second conductive layer. The second region does not include the first material or has a concentration of the first material which is lower than that in the first region.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Kanno, Tomofumi Zushi
  • Publication number: 20200083247
    Abstract: A semiconductor memory device according to an embodiment includes a base portion, a laminated body, a second conductive layer, and a columnar body. The columnar body includes a semiconductor body and a charge storage film. The semiconductor body includes a first region and a second region. The first region extends from a connection portion between the semiconductor body and the first semiconductor portion to the inside of the second conductive layer. The first region includes a first material. The second region is positioned closer to the laminated body than the first region is and is configured such that at least a portion is present within the second conductive layer. The second region does not include the first material or has a concentration of the first material which is lower than that in the first region.
    Type: Application
    Filed: February 21, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroshi KANNO, Tomofumi ZUSHI
  • Patent number: 10283522
    Abstract: According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: May 7, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tomofumi Zushi, Shinya Naito
  • Publication number: 20180277560
    Abstract: According to an embodiment, a semiconductor memory device includes a stacked body in which insulating layers and electrode films are alternately stacked, a pillar member arranged in a memory hole that is disposed in the stacked body in a thickness direction, and a semiconductor layer provided below the pillar member. The pillar member has a structure in which a memory film and a channel layer are stacked in order from a side of the stacked body. The channel layer has a stacked structure that includes an outer channel semiconductor layer, an intermediate layer made of an insulating material, and an inner channel semiconductor layer, from a side of the memory film. Both of the outer channel semiconductor layer and the inner channel semiconductor layer are electrically connected to the semiconductor layer.
    Type: Application
    Filed: September 6, 2017
    Publication date: September 27, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tomofumi Zushi, Shinya Naito