Patents by Inventor Tomofune Tani

Tomofune Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6048776
    Abstract: A method of fabricating a semiconductor device, comprises the steps of forming a trench in a semiconductor substrate by using a selective etching process; forming an insulating layer at least on the inner surface of the trench; forming a film containing silicon at least on the insulation layer in the trench and doping a first impurity of a first conductivity type by a first ion implantation to a predetermined depth of the semiconductor substrate at least through the film containing silicon, and wherein the first impurity doped into the semiconductor substrate by the first ion implantation is at a level deeper than the bottom of the trench.
    Type: Grant
    Filed: September 28, 1998
    Date of Patent: April 11, 2000
    Assignee: United Microelectronics
    Inventor: Tomofune Tani
  • Patent number: 5872392
    Abstract: A semiconductor fabrication process for forming a shield-plate electrode or a gate electrode in a trench to have the same conductivity type with each of adjacent p- and n-well regions includes steps for forming a trench in a semiconductor substrate by using a silicon nitride mask, forming an oxide film on the bottom of the trench, and filling a polysilicon film on the oxide film. In a selected region, outside the trench, an impurity of a desired conductivity type is doped by ion implantation to a predetermined depth of the semiconductor substrate. An impurity of the same conductivity type is further doped into the polysilicon film by shallowing the implantation level. In the adjacent region, an impurity of the opposite conductivity type is also doped into the polysilicon film and the semiconductor substrate outside the trench at different implantation levels.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: February 16, 1999
    Assignee: Nippon Steel Corporation
    Inventor: Tomofune Tani
  • Patent number: 5814887
    Abstract: A semiconductor device having a conductor film for inhibiting intrusion of moisture, mobile ions, etc. into a semiconductor chip from its peripheral edge, formed in a contact trench formed in an inter-layer insulating film. The conductor film divides the inter-layer insulating film into a peripheral edge side and an internal side and is moreover connected electrically to a semiconductor substrate. Therefore, any moisture or mobile ions entering the inter-layer insulating film from the peripheral edge of the semiconductor chip are electrically caught or expelled and cannot enter the semiconductor chip. Further, because the conductor film is formed inside the contact trench, the conductor film does not peel from the semiconductor chip even when any influences of the moisture or the mobile ions caught exist. An internal conductor can be insulated from outside by providing a protective film for covering the upper and said surfaces of the semiconductor chip.
    Type: Grant
    Filed: November 20, 1996
    Date of Patent: September 29, 1998
    Assignee: Nippon Steel Corporation
    Inventor: Tomofune Tani
  • Patent number: 5798545
    Abstract: A semiconductor substrate has two element forming regions and one element separation region between the two element forming regions. A shield electrode for electrically separating the two element forming regions is formed in the semiconductor substrate at the element separating region. A trench capacitor is formed in the semiconductor substrate at the element separation region. The trench capacitor has a trench, a first conductive layer covering at least the inner wall of the trench, a dielectric layer formed at least on the first conductive layer in the trench, and a second conductive layer formed at least on the dielectric layer in the trench. The shield electrode and the first conductive layer is made of the same layer. A transistor having a pair of impurity doped regions is formed in the semiconductor substrate at the element forming region, the second conductive layer of the trench capacitor is electrically connected to one of the pair of impurity doped regions of the transistor.
    Type: Grant
    Filed: December 27, 1995
    Date of Patent: August 25, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Shoichi Iwasa, Tomofune Tani
  • Patent number: 5578510
    Abstract: A method of making a semiconductor device includes forming of an element isolation layer stack on a first region of a silicon substrate between adjacent element forming regions and injecting impurity ions upon a surface of the silicon substrate so as to form a diffusion layer. The diffusion layer is formed to include a first portion disposed in a surface of the substrate just beneath the element isolation layer stack and at the same time a second portion disposed in the substrate inside each of the element forming regions at a depth which is at a distance from the surface of the substrate and deeper than the first portion.
    Type: Grant
    Filed: October 24, 1995
    Date of Patent: November 26, 1996
    Assignee: Nippon Steel Corporation
    Inventor: Tomofune Tani
  • Patent number: 5468979
    Abstract: A semiconductor device including a silicon substrate, an insulator film formed on said substrate, a transistor provided on said insulator film and a capacitor formed in a trench formed in said insulator film, and a method of manufacturing the same.
    Type: Grant
    Filed: August 23, 1994
    Date of Patent: November 21, 1995
    Assignee: Nippon Steel Corporation
    Inventors: Tomofune Tani, Ichiro Murai, Kenji Anzai
  • Patent number: 5432113
    Abstract: A method of manufacturing a semiconductor memory device including at least one memory cell having a transistor and a capacitor, forming at least one trench in a surface of a semiconductor substrate, forming a semiconductor film covering the surface of the semiconductor substrate and an inner wall of the trench, forming an oxidation-resistant film to cover at least a first part of the semiconductor film covering the inner wall of the trench including a bottom surface of the trench, and oxidizing a second part of the semiconductor film, which is not covered by the oxidation-resistant film, thereby to form an element isolation insulating film.
    Type: Grant
    Filed: August 4, 1993
    Date of Patent: July 11, 1995
    Assignee: Nippon Steel Corporation
    Inventor: Tomofune Tani
  • Patent number: 5290723
    Abstract: A method of manufacturing a nonvolatile semiconductor memory including forming a first insulating film, a first semiconductor film for forming floating gates, a second insulating film, and a second semiconductor film for forming control gates in that order on a semiconductor substrate, and forming etching masks, each having a configuration corresponding to that of the floating gate, at every other one of areas on the second semiconductor film where the floating gates are to be formed. Side wall spacers are formed on both side walls of each of the etching masks and a third semiconductor film, formed of the same material as that of the second semiconductor film is selectively grown on parts of the second semiconductor film which are not covered by any of the etching masks and the side wall spacers.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: March 1, 1994
    Assignee: Nippon Steel Corporation
    Inventors: Tomofune Tani, Kenji Anzai
  • Patent number: 5273928
    Abstract: A method of manufacturing a semiconductor memory device having trench capacitors comprises steps of, forming a trench in a semiconductor substrate, forming a first insulation film on a surface of the semiconductor substrate over at least a whole surface of inner walls of the trench, forming a resist layer within the trench having the surface formed with the first insulation film, the resist layer being destined for use as a mask for etching, removing selectively a portion of the first insulation film by etching by using the resist layer as a mask for the etching, removing the resist layer from the interior of the trench and forming a semiconductor film of a predetermined thickness over the surface of the semiconductor substrate and the side wall surfaces of the trench from which the first insulation film has been removed, oxidating selectively a portion of the semiconductor film, and forming a second insulation film for element isolation in continuation to the first insulation film while allowing other portio
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: December 28, 1993
    Assignee: Nippon Steel Corporation
    Inventor: Tomofune Tani