Patents by Inventor Tomofusa Shiga
Tomofusa Shiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230125063Abstract: A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.Type: ApplicationFiled: December 14, 2022Publication date: April 20, 2023Inventors: Seiji NOMA, Tomofusa SHIGA, Kouji SENDA, Tsuyoshi NISHIWAKI, Yuta FURUMURA, Akitaka SOENO
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Patent number: 10748988Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.Type: GrantFiled: July 8, 2019Date of Patent: August 18, 2020Assignee: DENSO CORPORATIONInventors: Masanori Miyata, Shigeki Takahashi, Masakiyo Sumitomo, Tomofusa Shiga
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Publication number: 20190333987Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.Type: ApplicationFiled: July 8, 2019Publication date: October 31, 2019Inventors: Masanori MIYATA, Shigeki TAKAHASHI, Masakiyo SUMITOMO, Tomofusa SHIGA
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Patent number: 9847409Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.Type: GrantFiled: July 14, 2015Date of Patent: December 19, 2017Assignee: DENSO CORPORATIONInventors: Tomofusa Shiga, Hiromitsu Tanabe
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Publication number: 20160020310Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.Type: ApplicationFiled: July 14, 2015Publication date: January 21, 2016Inventors: Tomofusa SHIGA, Hiromitsu TANABE
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Patent number: 9136333Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.Type: GrantFiled: January 18, 2012Date of Patent: September 15, 2015Assignee: DENSO CORPORATIONInventors: Takaaki Aoki, Tomofusa Shiga
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Publication number: 20150008478Abstract: A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration.Type: ApplicationFiled: January 22, 2013Publication date: January 8, 2015Inventors: Weitao Cheng, Shinji Amano, Yoshifumi Okabe, Tomofusa Shiga
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Patent number: 8614483Abstract: An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.Type: GrantFiled: December 7, 2011Date of Patent: December 24, 2013Assignee: DENSO CORPORATIONInventors: Hiromitsu Tanabe, Yukio Tsuzuki, Kenji Kouno, Tomofusa Shiga
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Publication number: 20120146091Abstract: An insulated gate semiconductor device includes a first conductivity-type semiconductor substrate, a second conductivity-type base layer on a first surface side of the substrate, a trench dividing the base layer into channel and floating layers, and a first conductivity-type emitter region that is formed in the channel layer and in contact with the trench. The semiconductor device includes a gate insulation layer in the trench, a gate electrode on the insulation layer, an emitter electrode electrically connected to the emitter region and the floating layer, a second conductivity-type collector layer in the substrate, and a collector electrode on the collector layer. The floating layer has a lower impurity concentration than the channel layer. The floating layer has a first conductivity-type hole stopper layer located at a predetermined depth from the first surface of the substrate and at least partially spaced from the insulation layer.Type: ApplicationFiled: December 7, 2011Publication date: June 14, 2012Applicant: DENSO CORPORATIONInventors: Hiromitsu Tanabe, Yukio Tsuzuki, Kenji Kouno, Tomofusa Shiga
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Publication number: 20120112273Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Applicant: DENSO CORPORATIONInventors: Takaaki AOKI, Tomofusa Shiga
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Patent number: 8154073Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.Type: GrantFiled: July 12, 2007Date of Patent: April 10, 2012Assignee: DENSO CORPORATIONInventors: Takaaki Aoki, Tetsuo Fujii, Tomofusa Shiga
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Patent number: 7800195Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.Type: GrantFiled: February 26, 2008Date of Patent: September 21, 2010Assignee: DENSO CORPORATIONInventors: Shoji Ozoe, Shoji Mizuno, Takaaki Aoki, Tomofusa Shiga
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Patent number: 7622768Abstract: On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.Type: GrantFiled: April 21, 2005Date of Patent: November 24, 2009Assignee: DENSO CORPORATIONInventors: Takaaki Aoki, Mikimasa Suzuki, Yukio Tsuzuki, Tomofusa Shiga
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Patent number: 7420246Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.Type: GrantFiled: May 30, 2006Date of Patent: September 2, 2008Assignee: DENSO CORPORATIONInventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
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Publication number: 20080203389Abstract: A semiconductor apparatus is provided. The semiconductor apparatus includes a semiconductor substrate and a temperature sensing diode that is disposed on a surface part of the semiconductor substrate. A relation between a forward current flowing through the temperature sensing diode and a corresponding voltage drop across the temperature sensing diode varies with temperature. The semiconductor apparatus further includes a capacitor that is coupled with the temperature sensing diode, configured to reduce noise to act on the temperature sensing diode, and disposed such that the capacitor and the temperature sensing diode have a layered structure in a thickness direction of the semiconductor substrate.Type: ApplicationFiled: February 26, 2008Publication date: August 28, 2008Applicant: DENSO CORPRORATIONInventors: Shoji Ozoe, Shoji Mizuno, Takaaki Aoki, Tomofusa Shiga
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Publication number: 20080012050Abstract: A semiconductor device includes: a semiconductor substrate; a vertical type trench gate MOS transistor; a Schottky barrier diode; multiple trenches having a stripe pattern to divide an inner region into first and second separation regions; and a poly silicon film in each trench. The first separation region includes a first conductive type region for providing a source and a second conductive type layer for providing a channel region. The first conductive type region is adjacent to a first trench. The poly silicon film in the first trench is coupled with a gate wiring. A second trench is not adjacent to the first conductive type region. The poly silicon film in the second trench is coupled with a source or gate wiring. The substrate in the second separation region is coupled with the source wiring for providing a Schottky barrier.Type: ApplicationFiled: July 12, 2007Publication date: January 17, 2008Applicant: DENSO CORPORATIONInventors: Takaaki Aoki, Tetsuo Fujii, Tomofusa Shiga
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Publication number: 20060273351Abstract: A vertical type semiconductor device includes: a silicon substrate having a first surface and a second surface; a first electrode disposed on the first surface of the silicon substrate; and a second electrode disposed on the second surface of the silicon substrate. Current is capable of flowing between the first electrode and the second electrode in a vertical direction of the silicon substrate. The second surface of the silicon substrate includes a re-crystallized silicon layer. The second electrode includes an aluminum film so that the aluminum film contacts the re-crystallized silicon layer with ohmic contact.Type: ApplicationFiled: May 30, 2006Publication date: December 7, 2006Applicant: DENSO CORPORATIONInventors: Shoji Ozoe, Tomofusa Shiga, Yoshifumi Okabe, Takaaki Aoki, Takeshi Fukazawa, Kimiharu Kayukawa
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Patent number: 6974996Abstract: In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.Type: GrantFiled: December 4, 2003Date of Patent: December 13, 2005Assignee: Denso CorporationInventors: Tomofusa Shiga, Takaaki Aoki, Yoshifumi Okabe
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Publication number: 20050236664Abstract: On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird's beak length by the silicon oxide film.Type: ApplicationFiled: April 21, 2005Publication date: October 27, 2005Inventors: Takaaki Aoki, Mikimasa Suzuki, Yukio Tsuzuki, Tomofusa Shiga
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Publication number: 20040145012Abstract: In a semiconductor device having a trench-gate structure in which polysilicon doped with boron is embedded in a trench, insulating film formed on the inner wall of the trench comprises ONO film, and silicon nitride film constituting the ONO film is formed to such film thickness and film quality that boron can be suppressed from passing through the silicon nitride film. Silicon oxide film is formed so that a top oxide film is thin and a bottom oxide film is thick.Type: ApplicationFiled: December 4, 2003Publication date: July 29, 2004Applicant: DENSO CORPORATIONInventors: Tomofusa Shiga, Takaaki Aoki, Yoshifumi Okabe