Patents by Inventor Tomoharu IKEDA
Tomoharu IKEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961701Abstract: When adjusting optical axes of a multi-beam charged particle beam device, because parameters of optical systems are inter-dependent, the time required to adjust the parameters increases. Thus, the present invention provides a charged particle beam device provided with an optical parameter setting unit for setting parameters of optical systems for emitting a plurality of primary charged particle beams to a sample, detectors for individually detecting a plurality of secondary charged particle beams discharged from the sample, a plurality of memories for storing signals detected by the detectors and converted into digital pixels in the form of images, evaluation value derivation units for deriving evaluation values of the primary charged particle beams from the images, and a GUI capable of displaying the images and receiving an input from a user, wherein the GUI displays the images and evaluation results based on the evaluation values and changes various optical parameters in real-time.Type: GrantFiled: April 24, 2019Date of Patent: April 16, 2024Assignee: HITACHI HIGH-TECH CORPORATIONInventors: Tomoharu Nagashima, Kazuki Ikeda, Wen Li, Masashi Wada, Hajime Kawano
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Patent number: 10319831Abstract: Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.Type: GrantFiled: February 25, 2015Date of Patent: June 11, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru Onishi, Shuhei Oki, Tomoharu Ikeda, Rahman Md. Tasbir
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Patent number: 10020390Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.Type: GrantFiled: August 4, 2014Date of Patent: July 10, 2018Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9853141Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.Type: GrantFiled: August 4, 2014Date of Patent: December 26, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9780205Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.Type: GrantFiled: August 4, 2014Date of Patent: October 3, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
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Patent number: 9755042Abstract: An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.Type: GrantFiled: February 10, 2015Date of Patent: September 5, 2017Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun Saito, Tomoharu Ikeda, Tomoyuki Shoji, Toshimasa Yamamoto
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Patent number: 9698017Abstract: A manufacturing method of a semiconductor device is provided by forming a trench in a surface of a SiC substrate, positioning a protective substrate to cover the trench, and annealing the SiC substrate and the protective substrate.Type: GrantFiled: February 29, 2016Date of Patent: July 4, 2017Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tomoharu Ikeda, Shinichiro Miyahara, Sachiko Aoi
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Publication number: 20170040446Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.Type: ApplicationFiled: August 4, 2014Publication date: February 9, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Publication number: 20170033195Abstract: Technique disclosed herein can suppress performance variation among semiconductor devices to be manufactured upon manufacturing each semiconductor device by forming diffusion layer by ion implantation to semiconductor substrate after etching. A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes an emitter region, a top body region, a barrier region, a bottom body region, a drift region, a collector region, a trench, a gate insulating film, and a gate electrode. A front surface of the gate electrode is provided at a deeper position than a front surface of the semiconductor substrate. Within the gate electrode, a front surface of a first portion at a widthwise center of a trench is provided at a shallower position than a front surface of a second portion in contact with the gate insulating film.Type: ApplicationFiled: February 25, 2015Publication date: February 2, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Toru ONISHI, Shuhei OKI, Tomoharu IKEDA, Rahman MD. TASBIR
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Publication number: 20170025516Abstract: An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.Type: ApplicationFiled: February 10, 2015Publication date: January 26, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Tomoharu IKEDA, Tomoyuki SHOJI, Toshimasa YAMAMOTO
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Publication number: 20170012121Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.Type: ApplicationFiled: August 4, 2014Publication date: January 12, 2017Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Publication number: 20160329422Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.Type: ApplicationFiled: August 4, 2014Publication date: November 10, 2016Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATIONInventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
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Publication number: 20160260608Abstract: A manufacturing method of a semiconductor device is provided by forming a trench in a surface of a SiC substrate, positioning a protective substrate to cover the trench, and annealing the SiC substrate and the protective substrate.Type: ApplicationFiled: February 29, 2016Publication date: September 8, 2016Inventors: Tomoharu Ikeda, Shinichiro Miyahara, Sachiko Aoi
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Patent number: 8659052Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. The diode region includes a first layer embedded in a diode trench reaching a diode drift layer from an upper surface side of the semiconductor substrate, and a second layer which is buried in the first layer and which has a lower end located deeper than a boundary between a diode body layer and the diode drift layer. The second layer pressures the first layer in a direction from inside to outside of the diode trench. A lifetime control region is formed in the diode drift layer at least at the depth of the lower end of the second layer, and a crystal defect density inside the lifetime control region is higher than a crystal defect density outside the lifetime control region.Type: GrantFiled: September 14, 2012Date of Patent: February 25, 2014Assignee: Toyota Jidosha Kabushiki KaishaInventor: Tomoharu Ikeda
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Publication number: 20130075784Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. The diode region includes a first layer embedded in a diode trench reaching a diode drift layer from an upper surface side of the semiconductor substrate, and a second layer which is buried in the first layer and which has a lower end located deeper than a boundary between a diode body layer and the diode drift layer. The second layer pressures the first layer in a direction from inside to outside of the diode trench. A lifetime control region is formed in the diode drift layer at least at the depth of the lower end of the second layer, and a crystal defect density inside the lifetime control region is higher than a crystal defect density outside the lifetime control region.Type: ApplicationFiled: September 14, 2012Publication date: March 28, 2013Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Tomoharu IKEDA