Patents by Inventor Tomoharu Mametani
Tomoharu Mametani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6787878Abstract: In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.Type: GrantFiled: August 4, 2000Date of Patent: September 7, 2004Assignee: Renesas Technology Corp.Inventors: Yukihiro Nagai, Tomoharu Mametani, Yoji Nakata, Shigenori Kido, Takeshi Kishida, Akinori Kinugasa, Hiroaki Nishimura, Jiro Matsufusa
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Publication number: 20040150030Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.Type: ApplicationFiled: December 31, 2003Publication date: August 5, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroaki Nishimura, Tomoharu Mametani, Yukihiro Nagai, Akinori Kinugasa, Takeshi Kishida
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Patent number: 6744143Abstract: A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.Type: GrantFiled: July 20, 2000Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Jiro Matsufusa, Tomoharu Mametani, Takeshi Kishida, Yoji Nakata, Yukihiro Nagai, Hiroaki Nishimura, Akinori Kinugasa, Shigenori Kido
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Patent number: 6673671Abstract: There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.Type: GrantFiled: November 28, 2000Date of Patent: January 6, 2004Assignee: Renesas Technology Corp.Inventors: Hiroaki Nishimura, Tomoharu Mametani, Yukihiro Nagai, Akinori Kinugasa, Takeshi Kishida
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Patent number: 6337268Abstract: A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).Type: GrantFiled: July 5, 2000Date of Patent: January 8, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenori Kido, Jiro Matsufusa, Tomoharu Mametani, Yoji Nakata, Takeshi Kishida, Yukihiro Nagai, Akinori Kinugasa, Hiroaki Nishimura
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Patent number: 6313005Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).Type: GrantFiled: July 5, 2000Date of Patent: November 6, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takeshi Kishida, Akinori Kinugasa, Yoji Nakata, Tomoharu Mametani, Shigenori Kido, Yukihiro Nagai, Hiroaki Nishimura, Jiro Matsufusa
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Patent number: 6251741Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC.Type: GrantFiled: December 23, 1998Date of Patent: June 26, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akinori Kinugasa, Tomoharu Mametani, Yukihiro Nagai, Hiroaki Nishimura, Takeshi Kishida
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Patent number: 6175156Abstract: An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower conducting layer is formed on a second interlayer insulating film. A third interlayer insulating film covers lower conducting layer. A contact hole is formed in third interlayer insulating film in order to connect an upper conducting layer and lower conducting layer. A stopper layer of silicide or metal is formed below contact hole between the surface of a semiconductor substrate and lower conducting layer.Type: GrantFiled: April 21, 1998Date of Patent: January 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoharu Mametani, Yukihiro Nagai
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Patent number: 6040615Abstract: On a semiconductor substrate, a first circuit and a second circuit are provided with a space therebetween. The first circuit and the second circuit are connected to each other by a fuse portion. In the middle of the fuse portion, a connecting portion is interposed, which is made of a material highly resistant to corrosion. Accordingly, an improved semiconductor device with a corrosion-resisting fuse portion is accomplished, which ensures the layout to be designed much more freely.Type: GrantFiled: April 14, 1998Date of Patent: March 21, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yukihiro Nagai, Tomoharu Mametani
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Patent number: 5770491Abstract: In a manufacturing process of a MOS FET having a C-MOS structure, lightly doped n- diffused layer is formed for source/drain regions in n channel and p channel transistor regions respectively. A p+ diffused layer is further formed for source/drain regions in a p channel transistor region. By a heating process, the n- layer is outweighed by diffusion of p type impurities in the p channel transistor region, and the source/drain current of the p channel MOS FET is secured.Type: GrantFiled: November 8, 1996Date of Patent: June 23, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tomoharu Mametani
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Patent number: 5478759Abstract: A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, having impurity concentration peak positions are formed in the region of silicon substrate positioned under the isolation oxide film. Then, an upper part of the isolation oxide film is removed away to form an isolation oxide film with a reduced thickness. Isolation oxide film has a reduced isolation length L. Thus, a semiconductor device is provided, which permits restriction of the narrow channel effect and the substrate biasing effect when the size of elements is reduced.Type: GrantFiled: November 24, 1993Date of Patent: December 26, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoharu Mametani, Masahiro Shimizu, Katsuhiro Tsukamoto, Hajime Arai, Heiji Kobayashi
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Patent number: 5289422Abstract: A are a semiconductor memory device excellent memory characteristics of which can be obtained without deteriorating a characteristic of a transistor for use in a peripheral circuit even when a memory cell array region and a peripheral circuit region differ from each other in wiring pattern density and a manufacturing method therefor. The semiconductor memory device includes a dummy pattern formed between and at predetermined distance from gate electrodes of a transfer gate transistor in the peripheral circuit region.Type: GrantFiled: October 29, 1991Date of Patent: February 22, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Tomoharu Mametani
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Patent number: 5234859Abstract: A LOCOS isolation film is formed on a major surface of a semiconductor substrate. Thereafter, a new surface of the semiconductor substrate is exposed by wet etching. A resist pattern is formed on the exposed new surface. A part of the LOCOS isolation film is removed using this resist pattern, to expose the surface of the semiconductor substrate. This unsymmetrical LOCOS isolation film increases the effective area of the surface of the semiconductor substrate and preserves predetermined dielectric resistance.Type: GrantFiled: September 3, 1991Date of Patent: August 10, 1993Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tomoharu Mametani, Ritsuko Tsutsumi, Ichiro Arimoto, Masami Yamamoto
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Patent number: 5168030Abstract: Disclosed herein is an antistatic photo-resist containing an antistatic agent. Since antistatic photo-resist according to the present invention is hardly charged, it can be suitably used as a mask in implanting ions into semiconductor substrate.Type: GrantFiled: August 5, 1991Date of Patent: December 1, 1992Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Kasei CorporationInventors: Konoe Miura, Tameichi Ochiai, Yasuhiro Kameyama, Tooru Koyama, Takashi Okabe, Tomoharu Mametani
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Patent number: 5065218Abstract: A LOCOS isolation film is formed on a major surface of a semiconductor substrate. Thereafter, a new surface of the semiconductor substrate is exposed by wet etching. A resist pattern is formed on the exposed new surface. A part of the LOCOS isolation film is removed using this resist pattern, to expose the surface of the semiconductor substrate. This unsymmetrical LOCOS isolation film increases the effective area of the surface of the semiconductor substrate and preserves predetermined dielectric resistance.Type: GrantFiled: June 23, 1989Date of Patent: November 12, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Ichiro Arimoto, Masami Yamamoto, Tomoharu Mametani, Ritsuko Tsutsumi, Ritsuko Tsutsumi, Ichiro Arimoto, Masami Yamamoto
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Patent number: 4933257Abstract: Disclosed herein is an antistatic photo-resist containing an antistatic agent. Since antistatic photo-resist according to the present invention is hardly charged, it can be suitably used as a mask in implanting ions into semiconductor substrate.Type: GrantFiled: September 18, 1989Date of Patent: June 12, 1990Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Chemical Industries LimitedInventors: Konoe Miura, Tameichi Ochiai, Yasuhiro Kameyama, Tooru Koyama, Takashi Okabe, Tomoharu Mametani