Abstract: A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Abstract: A synchronous DRAM is disclosed. The DRAM comprises an input buffer, a memory cell array, an output buffer, a signal transfer circuit, first and second latch circuits, and a controller. The input buffer receives an operation control signal supplied externally. The memory cell array has a plurality of memory cells for storing data. The output buffer outputs a data signal read from the memory cells. The signal transfer circuit reads a data signal from one of the memory cells in accordance with the operation control signal from the input buffer, and sends this read data signal to the output buffer. The first and second latch circuits, provided between the input buffer and the output buffer, latch the associated input signals in response to a clock signal.