Patents by Inventor Tomohide TEZUKA

Tomohide TEZUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Defect inspection apparatus and defect inspection method
    Patent number: 10943048
    Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Nojima, Tomohide Tezuka, Atsushi Onishi, Kazuhiro Yamada, Shigeki Nojima, Akira Hamaguchi
  • DEFECT INSPECTION APPARATUS AND DEFECT INSPECTION METHOD
    Publication number: 20200089838
    Abstract: An apparatus for inspecting a defect includes a memory storage and a processing unit coupled to the memory storage. The processing unit is configured to acquire pattern data for one or more patterns implemented on a wafer from a storage device, clip a portion that corresponds to the pattern data from a figure indicated by design data to generate design information and one or more circuit patterns, assign a first set of numbers to the one or more patterns of the pattern data, assign a second set of numbers to the one or more circuit patterns of the design information, generate relation information indicative of one or more correspondences between the first set of numbers and the second set of numbers, verify whether or not the one or more patterns indicated by the pattern data constitute a crucial defect based on the relation information, and send a verification result to a device.
    Type: Application
    Filed: February 28, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro NOJIMA, Tomohide TEZUKA, Atsushi ONISHI, Kazuhiro YAMADA, Shigeki NOJIMA, Akira HAMAGUCHI