Patents by Inventor Tomohiko Higashino

Tomohiko Higashino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110241169
    Abstract: A capacitor having a cylindrical shape is increased in capacitance, and a high-resistance region is prevented from being formed in a lower electrode. A semiconductor device includes a capacitor formed to have a cylindrical shape. The semiconductor device includes an insulating film formed over a substrate, a lower electrode formed to have a cylindrical shape, and including a first metal film which is not formed at a bottom portion in a depressed portion provided in the insulating film, but is selectively formed at a sidewall therein and a second metal film which is formed over the bottom portion in the depressed portion and over the first metal film at the sidewall therein, a capacitive film formed over the lower electrode, and an upper electrode formed over the capacitive film.
    Type: Application
    Filed: March 24, 2011
    Publication date: October 6, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: TOMOHIKO HIGASHINO
  • Publication number: 20080224196
    Abstract: A semiconductor device includes a first inverter, a second inverter, and an inner wiring connecting the inverters, in which the inner wiring forms a capacitor element, and the capacitor element includes an interlayer insulation film having an aperture on a semiconductor substrate, a lower electrode covering a bottom wall and a side wall of the aperture, the bottom wall being the semiconductor substrate and the side wall being a part of the interlayer insulation film, a capacitor insulation film arranged on the lower electrode and a part of the interlayer insulation film, the capacitor insulation film covering corners of the capacitor insulation film, the corners being situated at opposite side of the semiconductor substrate, and an upper electrode on the capacitor insulation film, the upper electrode covering the aperture.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 18, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomohiko HIGASHINO, Nobuyuki KATSUKI, Yasuhiro KAWAKATSU, Michihiro KOBAYASHI
  • Patent number: 6608344
    Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: August 19, 2003
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventor: Tomohiko Higashino
  • Patent number: 6514812
    Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: February 4, 2003
    Assignee: NEC Corporation
    Inventor: Tomohiko Higashino
  • Publication number: 20020185672
    Abstract: In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom, an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has an sharpened tip end and an inclined surface descending from the sharpened tip end toward each adjacent cylindrical lower electrode. With this arrangement, it is possible to prevent silicon grains of a hemi-spherical grain silicon from nidating on the partition, thereby prevent a short-circuiting between the adjacent cylindrical lower electrodes, without reducing the capacitance of the memory cell.
    Type: Application
    Filed: July 29, 2002
    Publication date: December 12, 2002
    Applicant: NEC CORPORATION
    Inventor: Tomohiko Higashino
  • Patent number: 6426527
    Abstract: In a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom, an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has an sharpened tip end and an inclined surface descending from the sharpened tip end toward each adjacent cylindrical lower electrode. With this arrangement, it is possible to prevent silicon grains of a hemi-spherical grain silicon from nidating on the partition, thereby prevent a short-circuiting between the adjacent cylindrical lower electrodes, without reducing the capacitance of the memory cell.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: July 30, 2002
    Assignee: NEC Corporation
    Inventor: Tomohiko Higashino
  • Publication number: 20020038881
    Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.
    Type: Application
    Filed: December 6, 2001
    Publication date: April 4, 2002
    Inventor: Tomohiko Higashino
  • Publication number: 20010008789
    Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.
    Type: Application
    Filed: January 16, 2001
    Publication date: July 19, 2001
    Applicant: Nec Corporation
    Inventor: Tomohiko Higashino