Patents by Inventor Tomohiko Mori

Tomohiko Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11969884
    Abstract: A gripping mechanism (3) includes a gripping roller (32) and a holder (31) that houses the gripping roller (32). A gripped portion (42) of a first component (4) is gripped between an outer surface of the gripping roller (32) and an inner surface of the holder (31) through action of gravity acting on the gripping roller (32). Preferably, the gripping roller (32) includes a core (321) that is cylindrical or columnar in shape and a covering section (322) that is an elastic body covering a circumferential surface of the core (321). Preferably, the covering section (322) has a circumferential surface with a friction coefficient greater than a friction coefficient of the circumferential surface of the core (321).
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 30, 2024
    Assignee: KYOCERA Document Solutions Inc.
    Inventors: Tomohiko Yamakawa, Koji Izumi, Masaru Takagi, Hayato Mori
  • Publication number: 20230211325
    Abstract: A catalyst structure for synthesis gas production of a synthesis gas that contains carbon monoxide and hydrogen, the catalyst structure being provided with a carrier that has a porous structure, while being configured from a zeolite type compound; first catalyst particles that contain one or more iron group elements which are selected from the group consisting of nickel (Ni), iron (Fe) and cobalt (Co); and second catalyst particles that contain one or more platinum group elements which are selected from the group consisting of platinum (Pt), palladium (Pd), rhodium (Rh) and ruthenium (Ru). The catalyst structure for synthesis gas production has passages in communication with each other within the carrier. The first catalyst particles are present at least in the passages of the carrier; and the second catalyst particles are present at least either inside the carrier or on the outer surface of the carrier.
    Type: Application
    Filed: June 1, 2021
    Publication date: July 6, 2023
    Applicants: FURUKAWA ELECTRIC CO., LTD., NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Yuichiro BANBA, Masayuki FUKUSHIMA, Takahiro UENO, Tomohiko MORI, Mai NISHII, Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA
  • Publication number: 20220238703
    Abstract: A semiconductor device includes a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer has an element part and a peripheral withstand voltage part. The source electrode is disposed adjacent to a first main surface of the nitride semiconductor layer. The drain electrode is disposed adjacent to a second main surface of the nitride semiconductor layer. The nitride semiconductor layer is formed with a first groove on the first main surface in the element part, and a second groove on the first main surface in the peripheral withstand voltage part. A JFET region is embedded in the first groove in the element part. An inclination angle of a side surface of the first groove adjacent to a channel portion of a body region is smaller than an inclination angle of a side surface of the second groove.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Hirofumi KIDA, Hidemoto TOMITA, Tomohiko MORI, Hideya YAMADERA
  • Publication number: 20220161242
    Abstract: Provided is a synthesis gas production catalyst structure or the like which can maintain stable high catalytic activity for a long period of time without degradation and can allow efficient production of a synthesis gas including carbon monoxide and hydrogen. The synthesis gas production catalyst structure 1 for use in producing a synthesis gas comprising carbon monoxide and hydrogen, the synthesis gas production catalyst structure 1 including: supports 10 each having a porous structure and including a zeolite-type compound; and at least one catalytic material 20 present in the supports 10, in which each of the supports 10 has channels 11 communicating with one another, each of the supports 10 has a ratio (L/d ratio) of long side dimension L to thickness dimension d of 5.0 or more, and the catalytic material 20 is present at least in the channel 11 of each of the supports 10.
    Type: Application
    Filed: December 3, 2019
    Publication date: May 26, 2022
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yuichiro BANBA, Kaori SEKINE, Yukako NAKAI, Mai NISHII, Masayuki FUKUSHIMA, Sadahiro KATO, Atsushi SHIMOYAMADA, Tomohiko MORI, Takao MASUDA, Yuta NAKASAKA, Takuya YOSHIKAWA
  • Patent number: 11328851
    Abstract: A method of manufacturing a ceramic electronic component such that Voids of the ceramic element and voids at the interfaces between the ceramic element and the external electrodes are filled with a resin composition by applying, to the ceramic electronic component, a resin-containing solution that has the function of etching the surface of the ceramic element to ionize constituent elements of the ceramic element. The resin composition includes a resin, and cationic elements among the constituent elements of the ceramic elements, which are ionized and deposited from the ceramic element.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: May 10, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mitsunori Inoue, Tomohiko Mori
  • Publication number: 20220024814
    Abstract: A surface-modified glass that includes glass containing at least one multivalent metal ion; and a silicate film on a surface of the glass, the silicate film containing a multivalent metal ion in common with that of the glass.
    Type: Application
    Filed: October 7, 2021
    Publication date: January 27, 2022
    Inventors: Noriyuki Ookawa, Yoshiyuki Nomura, Tomohiko Mori
  • Patent number: 11107691
    Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 31, 2021
    Assignee: DENSO CORPORATION
    Inventors: Toru Ikeda, Tomohiko Mori, Narumasa Soejima, Hideya Yamadera
  • Patent number: 10997934
    Abstract: Image display control by which effective correction is performed even for a biased change in a source potential for one frame in a liquid crystal display device is achieved. A liquid crystal display device (2) includes a correction unit that corrects a source voltage value to a pixel. The correction unit calculates a correction amount by using an integrated value of a source potential for previous one frame instead of an integrated value of the source potential for next one frame. The liquid crystal display device (2) applies the source voltage based on the correction amount to the pixel.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: May 4, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tomohiko Mori
  • Patent number: 10971619
    Abstract: A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 6, 2021
    Assignee: DENSO CORPORATION
    Inventors: Hidemoto Tomita, Tomohiko Mori
  • Publication number: 20200365409
    Abstract: A method of manufacturing a semiconductor device is provided, and the method may include: preparing a semiconductor substrate constituted of a group III nitride semiconductor, a main surface of the semiconductor substrate being a c-plane; forming a grove on the main surface by dry dry-etching the main surface; and wet-etching an inner surface of the groove using an etchant to expose the c-plane of the semiconductor substrate in a wet-etched region, the etching having an etching rate to the c-plane of the semiconductor substrate that is lower than the etching rate to a plane other than the c-plane of the semiconductor substrate.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 19, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Toru IKEDA, Tomohiko Mori, Narumasa Soejima, Hideya Yamadera
  • Publication number: 20200327856
    Abstract: Image display control by which effective correction is performed even for a biased change in a source potential for one frame in a liquid crystal display device is achieved. A liquid crystal display device (2) includes a correction unit that corrects a source voltage value to a pixel. The correction unit calculates a correction amount by using an integrated value of a source potential for previous one frame instead of an integrated value of the source potential for next one frame. The liquid crystal display device (2) applies the source voltage based on the correction amount to the pixel.
    Type: Application
    Filed: October 26, 2018
    Publication date: October 15, 2020
    Inventor: TOMOHIKO MORI
  • Patent number: 10650955
    Abstract: An electronic component includes a main body composed of an insulator, a coating film covering the main body, a circuit element located inside the main body, and outer electrodes. The insulator contains a metal magnetic powder. The coating film is composed of a resin and a cationic element contained in the insulator.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironobu Kubota, Mitsunori Inoue, Tomohiko Mori, Gota Shinohara, Kenji Nishiyama
  • Publication number: 20200052104
    Abstract: A semiconductor device may include a semiconductor layer; a source electrode disposed above one main surface of the semiconductor layer; a drain electrode disposed below another main surface of the semiconductor layer; and an insulation gate section. The semiconductor layer may include a drift region of a first conductivity type; a JFET region of the first conductivity type disposed above the drift region; a body region of a second conductivity type disposed above the drift region and adjoining the JFET region; and a source region of the first conductivity type separated from the JFET region by the body region. The insulation gate section may be opposed to a portion of the body region that separates the JFET region and the source region, a space may be provided within the semiconductor layer, and the drift region, the JFET region and the body region may be exposed to the space.
    Type: Application
    Filed: July 3, 2019
    Publication date: February 13, 2020
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidemoto Tomita, Tomohiko Mori
  • Patent number: 10553343
    Abstract: An electronic component includes a main body composed of an insulator, a coating film covering the main body, a circuit element located inside the main body, and outer electrodes. The insulator contains a metal magnetic powder. The coating film is composed of a resin and a cationic element contained in the insulator.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 4, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironobu Kubota, Mitsunori Inoue, Tomohiko Mori, Gota Shinohara, Kenji Nishiyama
  • Patent number: 10475567
    Abstract: An electronic component includes a main body composed of an insulator, a coating film covering the main body, a circuit element located inside the main body, and outer electrodes. The insulator contains a metal magnetic powder. The coating film is composed of a resin and a cationic element contained in the insulator.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 12, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hironobu Kubota, Mitsunori Inoue, Tomohiko Mori, Gota Shinohara, Kenji Nishiyama
  • Publication number: 20190305124
    Abstract: A semiconductor device includes an n-type first drift layer, an i-type or an n-type withstand voltage layer disposed on top of the first drift layer, a p-type body layer disposed on top of the withstand voltage layer, an n-type second drift layer that is disposed on top of the first drift layer, is in contact with side surfaces of the withstand voltage layer and the body layer, an n-type source layer that is disposed on top of the body layer, is separated from the first drift layer, the second drift layer, and the withstand voltage layer by the body layer, and a gate electrode that faces the body layer through a gate insulating film, the body layer being positioned between the second drift layer and the source layer. The withstand voltage layer is made from a material having a bandgap larger than that of the first drift layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: October 3, 2019
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi WATANABE, Hiroyuki UEDA, Tomohiko MORI
  • Patent number: 10326012
    Abstract: A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, and a gate electrode disposed on the semiconductor substrate via a gate insulator film. The semiconductor substrate includes a first portion constituted of GaN and a second portion constituted of AlxGa(1-x)N (0<x?1). The first portion includes an n-type source region being in contact with the source electrode, an n-type drain region being in contact with the drain electrode, a p-type body region intervening between the source region and the drain region and being in contact with the source electrode, and an n-type drift region intervening between the body region and the drain region and having a carrier density that is lower than a carrier density of the drain region. The second portion includes a barrier region being in contact with each of the source electrode, the body region and the drift region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Atsushi Watanabe, Hiroyuki Ueda, Tomohiko Mori
  • Patent number: 10324337
    Abstract: A liquid crystal display device according to the present invention has a display area that includes a plurality of pixels (Px). The display area is made up of n kinds of domains (where n is an integer that is equal to or greater than two and equal to or smaller than four). The directors of the n kinds of domains define mutually different alignment directions. If the domain structure of each pixel (Px) is defined by the kinds of the domains that form the pixel (Px), the number k of the kinds of the domains that form the pixel (Px), and the arrangement of the domains in the pixel (Px), the display area includes a pixel, of which k is less than n and of which the domain structure is different from the domain structures of adjacent pixels.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: June 18, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Isamu Miyake, Tomohiko Mori, Iichiroh Inoue
  • Patent number: 10312362
    Abstract: A switching element includes a semiconductor substrate that includes a first n-type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 4, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tetsuya Yamada, Takashi Okawa, Tomohiko Mori, Hiroyuki Ueda
  • Patent number: 10304630
    Abstract: A ceramic electronic component that includes a ceramic element, and a coating film and external electrodes that are provided on the surface of the ceramic element. The coating film is selectively formed on the surface of the ceramic element by applying, to the ceramic electronic component, a resin-containing solution containing at least one anion of a sulfuric acid, a sulfonic acid, a carboxylic acid, a phosphoric acid, a phosphoric acid, and a hydrofluoric acid.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: May 28, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Mitsunori Inoue, Tomohiko Mori