Patents by Inventor Tomohiko Murase

Tomohiko Murase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411672
    Abstract: An elastic wave device includes a piezoelectric substrate, IDT electrodes disposed on the piezoelectric substrate, a first wiring line, an insulating layer covering at least a portion of the first wiring line, a second wiring line at least a portion of which is disposed on the insulating layer to provide a three-dimensional crossing portion, a peripheral support including a cavity surrounding the IDT electrodes, the first and second wiring lines, and the insulating layer, a partition support disposed in the cavity, and a cover disposed on the peripheral support and the partition support to cover the cavity. The second wiring line includes a step portion electrically connecting a portion of the second wiring line located on the piezoelectric substrate and a portion of the second wiring line located on the insulating layer to each other. The partition support covers the step portion.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: September 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiko Murase
  • Patent number: 10050601
    Abstract: An elastic wave apparatus includes a piezoelectric substrate, an IDT electrode on the piezoelectric substrate and includes first electrode fingers, second electrode fingers, a first busbar, and a second busbar, a capacitive electrode including third electrode fingers, fourth electrode fingers, a third busbar, and a fourth busbar, an insulating film laminated on the capacitive electrode, a first wiring line including a first portion facing the capacitive electrode via the insulating film, and a second wiring line that connects the first busbar and the third busbar. The capacitive electrode extends in a lateral direction with respect to the IDT electrode in a surface acoustic wave propagation direction.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 14, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomohiko Murase
  • Publication number: 20170373667
    Abstract: An elastic wave device includes a piezoelectric substrate, IDT electrodes disposed on the piezoelectric substrate, a first wiring line, an insulating layer covering at least a portion of the first wiring line, a second wiring line at least a portion of which is disposed on the insulating layer to provide a three-dimensional crossing portion, a peripheral support including a cavity surrounding the IDT electrodes, the first and second wiring lines, and the insulating layer, a partition support disposed in the cavity, and a cover disposed on the peripheral support and the partition support to cover the cavity. The second wiring line includes a step portion electrically connecting a portion of the second wiring line located on the piezoelectric substrate and a portion of the second wiring line located on the insulating layer to each other. The partition support covers the step portion.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 28, 2017
    Inventor: Tomohiko MURASE
  • Publication number: 20170279432
    Abstract: An elastic wave apparatus includes a piezoelectric substrate, an IDT electrode on the piezoelectric substrate and includes first electrode fingers, second electrode fingers, a first busbar, and a second busbar, a capacitive electrode including third electrode fingers, fourth electrode fingers, a third busbar, and a fourth busbar, an insulating film laminated on the capacitive electrode, a first wiring line including a first portion facing the capacitive electrode via the insulating film, and a second wiring line that connects the first busbar and the third busbar. The capacitive electrode extends in a lateral direction with respect to the IDT electrode in a surface acoustic wave propagation direction.
    Type: Application
    Filed: June 14, 2017
    Publication date: September 28, 2017
    Inventor: Tomohiko MURASE
  • Patent number: 7531962
    Abstract: To maximize the efficiency of utilization of mother substrates used as material for the substrates in the flat display panel to form a display screen, the flat display panel includes a display screen formed by tetragonal first and second substrates. Four sides or opposite two sides forming a tetragonal peripheral edge of the first substrate are rendered to be substantially equal to those of the second substrate, and the first and second substrate are sandwiched together with one of the first and second substrates protruding in part outwardly from the peripheral edge of the other of the first and second substrates.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: May 12, 2009
    Assignee: Fujitsu Hitachi Plasma Display Limited
    Inventors: Yasuhiko Kunii, Hiroyuki Nakahara, Tomohiko Murase, Fumihiro Namiki
  • Publication number: 20090021167
    Abstract: A technology capable of preventing or suppressing a display defect in a PDP (detrimental effect due to local contamination of the display area caused by admixture of impurity gas at the time of introducing discharge gas) is provided. In a PDP, first barrier ribs and first phosphors formed between the first barrier ribs are provided so as to correspond to a display area. In a non-display area outside the display area, an air hole for evacuation from a discharge space and gas filling into the discharge space is provided in a part of an outer perimeter of the panel. Further, an area in which second phosphors having a property of absorbing impurity gas are formed is formed at a position between the display area and the air hole in a part of the non-display area, in particular, in a part of a dummy rib area.
    Type: Application
    Filed: July 15, 2008
    Publication date: January 22, 2009
    Inventors: Koji OHIRA, Tomohiko Murase, Minoru Fukui, Taisuke Yamamoto
  • Publication number: 20080145517
    Abstract: A method for manufacturing a plasma display comprises: a phosphor painting process for painting phosphor layer in ribs formed on a back plate; and a phosphor inspection process that includes the steps of: irradiating the phosphor layer with ultraviolet light; preparing an imaging system so that the imaging system images the emitted light beam to acquire information on brightness; comparing the brightness information with correlation between a shape model of the phosphor layer and brightness signal information that have been obtained in advance; and obtaining a painted state of the phosphor layer painted in the ribs; and a process for feeding back the applied state of the phosphor layer, which has been obtained in the phosphor inspection process, to the phosphor painting process so that the manufacturing equipment is controlled in the phosphor painting process.
    Type: Application
    Filed: August 6, 2007
    Publication date: June 19, 2008
    Inventors: Hideaki SASAZAWA, Mineo Nomoto, Kouji Kashiwagi, Shigeru Saitou, Tomohiko Murase
  • Patent number: 7223316
    Abstract: A method for manufacturing an electronic component includes the steps of inserting tabs of a cover into through holes formed in a circuit board having mounting elements on the front surface thereof, disposing a print mask having openings at positions corresponding to the through holes on the back surface of the circuit board, and supplying solder cream to the through holes through the openings by placing the solder cream on the print mask and moving the solder cream in a predetermined direction with a squeegee. The print mask is provided with projections which project upstream in the moving direction of the solder cream in openings of the print mask, and the openings are shifted upstream in the moving direction of the solder cream. In addition, the tabs are inserted into the through holes such that the width direction of the tabs is along the moving direction of the solder cream.
    Type: Grant
    Filed: January 13, 2004
    Date of Patent: May 29, 2007
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Tomohiko Murase
  • Publication number: 20050110411
    Abstract: To maximize the efficiency of utilization of mother substrates used as material for the substrates in the flat display panel to form a display screen, the flat display panel includes a display screen formed by tetragonal first and second substrates. Four sides or opposite two sides forming a tetragonal peripheral edge of the first substrate are rendered to be substantially equal to those of the second substrate, and the first and second substrate are sandwiched together with one of the first and second substrates protruding in part outwardly from the peripheral edge of the other of the first and second substrates.
    Type: Application
    Filed: August 30, 2004
    Publication date: May 26, 2005
    Applicant: FUJITSU HITACHI PLASMA DISPLAY LIMITED
    Inventors: Yasuhiko Kunii, Hiroyuki Nakahara, Tomohiko Murase, Fumihiro Namiki
  • Patent number: 6840833
    Abstract: In the manufacture of a gas discharge type display panel, by applying a sealing operation along with an exhausting operation, the sealing glass 14 is broken down by a pressure difference between the inside and outside of the panel, and thus, the clearance gap between the substrates can be controlled as desired. In addition, the gaseous component that is unnecessary for the discharge operation is exhausted by setting the temperature of the amorphous sealing glass to exceed its softening-point and be no more than its working point. In the structure of the gas discharge type display panel, a protruding portion having a radius of curvature between 0.1 mm and 1 mm is formed on the sealing glass to reduce the dispersion in the thickness direction of the sealing glass, or the cross-sectional shape of the sealing glass is made convex both at its inside end part and its outside end part.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: January 11, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Shigehisa Motowaki, Tomohiko Murase, Michifumi Kawai, Ryohei Sato, Yasuhiro Matsuoka, Yoshihiro Kato, Takashi Naito, Yasutaka Suzuki
  • Publication number: 20040159396
    Abstract: A method for manufacturing an electronic component includes the steps of inserting tabs of a cover into through holes formed in a circuit board having mounting elements on the front surface thereof, disposing a print mask having openings at positions corresponding to the through holes on the back surface of the circuit board, and supplying solder cream to the through holes through the openings by placing the solder cream on the print mask and moving the solder cream in a predetermined direction with a squeegee. The print mask is provided with projections which project upstream in the moving direction of the solder cream in openings of the print mask, and the openings are shifted upstream in the moving direction of the solder cream. In addition, the tabs are inserted into the through holes such that the width direction of the tabs is along the moving direction of the solder cream.
    Type: Application
    Filed: January 13, 2004
    Publication date: August 19, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Tomohiko Murase
  • Patent number: 6621217
    Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
  • Publication number: 20020070665
    Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.
    Type: Application
    Filed: February 11, 2002
    Publication date: June 13, 2002
    Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
  • Patent number: 6346772
    Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: February 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
  • Publication number: 20020014841
    Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.
    Type: Application
    Filed: July 13, 2001
    Publication date: February 7, 2002
    Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
  • Patent number: 6333599
    Abstract: A plasma display system has a plasma display panel including a pair of base plates for forming a plurality of discharge cells therebetween, and a plurality of pairs of electrodes for sustaining discharge to form plasma through a dielectric substance thereon in the discharge cells. The pairs of electrodes for sustaining discharge are disposed on a same one of the pair of base plates. The plasma display panel is configured such that a discharge current integrated over 40% of a discharge time Td from a start of the discharge time Td is smaller than a discharge current integrated over a remainder of the discharge time Td in one discharge, wherein the discharge time Td is defined as a time interval over which a discharge current does not drop to less than 5% of its maximum value in one discharge.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: December 25, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Yoshimi Kawanami, Keizo Suzuki, Kenichi Yamamoto, Shirun Ho, Masaji Ishigaki, Ryohei Satoh, Masayuki Shibata, Tomohiko Murase, Michifumi Kawai
  • Patent number: 6261144
    Abstract: A gas discharge display device comprising a front side substrate having a plurality of first electrodes and a back side substrate having a plurality of second electrodes, wherein at least said first electrodes or second electrodes are formed by wet etching using a resist made of an inorganic material, is excellent in the ability to suppress the breakage of wiring in electrodes.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: July 17, 2001
    Assignee: Hitachi, LTD
    Inventors: Masashi Nishiki, Ryohei Satoh, Yuzo Taniguchi, Shigeaki Suzuki, Michifumi Kawai, Masahito Ijuin, Akira Yabushita, Makoto Fukushima, Tomohiko Murase
  • Patent number: 6199404
    Abstract: A manufacturing method for a gas discharge type display panel makes it possible to manufacture an environmentally friendly substrate with high accuracy and yet at low cost. According to the manufacturing methods electrodes are formed on a back substrate by photolithography or printing, then a glass paste is printed to a height of approximately 10 &mgr;m-500 &mgr;m by printing. A barrier rib blanks are produced by rolling under pressure the glass paste by using a roller provided with grooves. The roller is heated in advance. The barrier rib blanks are sintered into the barrier ribs.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: March 13, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Michifumi Kawai, Ryohei Satoh, Masahito Ijuin, Tomohiko Murase, Takao Terabayashi, Nobuyuki Ushifusa, Yoshihiro Kato, Shigeaki Suzuki, Seiichi Tsuchida, Yutaka Naito, Seiichi Yasumoto, Osami Kaneto