Patents by Inventor Tomohiko Sugimoto

Tomohiko Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806728
    Abstract: An amplifier circuit includes a sampling circuit and an amplifier connected to an output of the sampling circuit. A feedback capacitor is between an output terminal of the amplifier and an output terminal of the sampling circuit. A quantizer that includes a comparator is configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of a voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal of the comparator. The quantizer outputs a digital code according to the voltage comparison. A control circuit receives the digital code from the quantizer and stores the digital code in a register as a cancellation digital code. A digital-analog (D/A) converter outputs an analog signal in accordance with digital codes from the control circuit.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka
  • Patent number: 9685974
    Abstract: A switched capacitor circuit includes a first sampling circuit having a first sampling capacitance element. The first sampling circuit receives an input voltage and outputs a sampled voltage according to a first sampling operation. A quantizer quantizes the sampled voltage output from the first sampling circuit and outputs a quantized value corresponding to the sampled voltage. A digital-to-analog converter outputs an analog signal in accordance with the quantized value from the quantizer. A first logic circuit outputs an instruction to start a sampling operation of a second sampling circuit, which is configured to sample the analog signal output from the digital-to-analog converter, when the quantizer completes quantization of the sampled voltage.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka
  • Patent number: 9634627
    Abstract: According to one embodiment, an amplification circuit includes a differential amplifier and a feedback circuit. The differential amplifier includes a sampling circuit that samples a first voltage which is a difference between an adjustment voltage supplied to a first terminal and a first input voltage, and a second voltage which is a difference between the adjustment voltage and a second input voltage. The differential amplifier amplifies the first voltage to output a first voltage signal and amplifies the second voltage to output a second voltage signal. The feedback circuit detects a common mode voltage of the first voltage signal and the second voltage signal, and adjusts the adjustment voltage which is supplied to the first terminal in accordance with the common mode voltage.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: April 25, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii
  • Patent number: 9606511
    Abstract: According to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii
  • Publication number: 20160359463
    Abstract: According to one embodiment, an amplification circuit includes a differential amplifier and a feedback circuit. The differential amplifier includes a sampling circuit that samples a first voltage which is a difference between an adjustment voltage supplied to a first terminal and a first input voltage, and a second voltage which is a difference between the adjustment voltage and a second input voltage. The differential amplifier amplifies the first voltage to output a first voltage signal and amplifies the second voltage to output a second voltage signal. The feedback circuit detects a common mode voltage of the first voltage signal and the second voltage signal, and adjusts the adjustment voltage which is supplied to the first terminal in accordance with the common mode voltage.
    Type: Application
    Filed: March 9, 2016
    Publication date: December 8, 2016
    Inventors: Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii
  • Publication number: 20160274546
    Abstract: According to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 22, 2016
    Inventors: Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii
  • Patent number: 9413373
    Abstract: According to one embodiment, an amplifier circuit includes a first converter generating a time signal by voltage-time converting an input signal; a second converter generating an output signal by time-voltage converting the time signal; and a correction circuit outputting a control signal by comparing the time signal and a reference signal. The first converter generates the time signal, based on the control signal.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotomo Ishii, Daisuke Kurose, Tomohiko Sugimoto
  • Patent number: 9140229
    Abstract: A knocking control system comprises a knocking determiner device for determining whether or not knocking with a predetermined intensity or higher has occurred in a cylinder of a gas engine in each cycle; an integration variable calculator which adds to an integration variable CT when the knocking determiner device determines that the knocking with the predetermined intensity or higher has occurred, and subtracts from the integration variable CT when the knocking determiner determines that the knocking with the predetermined intensity or higher has not occurred; and a main controller for reducing a power output of the cylinder if the integration variable CT is not less than a threshold.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: September 22, 2015
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto, Tetsuo Tokuoka, Hiroyoshi Ishii
  • Patent number: 8988268
    Abstract: According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Sugimoto, Hirotomo Ishii
  • Patent number: 8983755
    Abstract: A control system for controlling a power output of a gas engine of the present invention includes a target value setting section for setting as a target value a restricted power output which is less than a predetermined power output when a source gas pressure of a gas fuel is less than a predetermined value required to inject the gas fuel against an intake-air pressure according to the predetermined power output, a power output setting section for setting a set value of a power output based on the target value set by the target value setting section, and a power output control section for controlling the power output so that the power output reaches the set value set by the power output setting section.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: March 17, 2015
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto
  • Patent number: 8783226
    Abstract: A knocking control system for a gas engine of the present invention, being configured to calculate a knocking occurrence ratio (SEV) which is a ratio of a cycle number of cycles in which a predetermined knocking occurs for a period of the cycles of the predetermined cycle number, to the predetermined cycle number, decide a target value of an ignition timing of the ignition device based on a deviation (?SEV) between an occurrence ratio delay calculation value (SEVAVE) obtained by performing delay calculation of the knocking occurrence ratio and a predetermined occurrence ratio target value (SEVSET), and drive the ignition device so that the ignition timing reaches a command value (IGN) decided according to the target value.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 22, 2014
    Assignee: Kawasaki Jukogyo Kabushiki Kaisha
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto, Tetsuo Tokuoka, Hiroyoshi Ishii
  • Publication number: 20140145868
    Abstract: According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.
    Type: Application
    Filed: September 9, 2013
    Publication date: May 29, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiko Sugimoto, Hirotomo Ishii
  • Patent number: 8730083
    Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotomo Ishii, Tomohiko Sugimoto, Masanori Furuta
  • Patent number: 8659454
    Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiko Sugimoto, Takafumi Yamaji, Junya Matsuno, Masanori Furuta
  • Publication number: 20130182803
    Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.
    Type: Application
    Filed: September 11, 2012
    Publication date: July 18, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirotomo Ishii, Tomohiko Sugimoto, Masanori Furuta
  • Publication number: 20130076545
    Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 28, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiko Sugimoto, Takafumi Yamaji, Junya Matsuno, Masanori Furuta
  • Publication number: 20120310510
    Abstract: A control system for controlling a power output of a gas engine of the present invention includes a target value setting section for setting as a target value a restricted power output which is less than a predetermined power output when a source gas pressure of a gas fuel is less than a predetermined value required to inject the gas fuel against an intake-air pressure according to the predetermined power output, a power output setting section for setting a set value of a power output based on the target value set by the target value setting section, and a power output control section for controlling the power output so that the power output reaches the set value set by the power output setting section.
    Type: Application
    Filed: December 22, 2010
    Publication date: December 6, 2012
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto
  • Publication number: 20110259298
    Abstract: A knocking control system for a gas engine of the present invention, being configured to calculate a knocking occurrence ratio (SEV) which is a ratio of a cycle number of cycles in which a predetermined knocking occurs for a period of the cycles of the predetermined cycle number, to the predetermined cycle number, decide a target value of an ignition timing of the ignition device based on a deviation (?SEV) between an occurrence ratio delay calculation value (SEVAVE) obtained by performing delay calculation of the knocking occurrence ratio and a predetermined occurrence ratio target value (SEVSET), and drive the ignition device so that the ignition timing reaches a command value (IGN) decided according to the target value.
    Type: Application
    Filed: September 17, 2009
    Publication date: October 27, 2011
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto, Tetsuo Tokuoka, Hiroyoshi Ishii
  • Publication number: 20110224889
    Abstract: A knocking control system comprises a knocking determiner device for determining whether or not knocking with a predetermined intensity or higher has occurred in a cylinder of a gas engine in each cycle; an integration variable calculator which adds to an integration variable CT when the knocking determiner device determines that the knocking with the predetermined intensity or higher has occurred, and subtracts from the integration variable CT when the knocking determiner determines that the knocking with the predetermined intensity or higher has not occurred; and a main controller for reducing a power output of the cylinder if the integration variable CT is not less than a threshold.
    Type: Application
    Filed: September 1, 2009
    Publication date: September 15, 2011
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto, Tetsuo Tokuoka, Hiroyoshi Ishii
  • Publication number: 20110214649
    Abstract: A control system for a gas engine including a controller being configured to execute load equalization control such that a fuel feed amount corresponding to a higher-temperature cylinder of a first predetermined number which is selected to include a highest exhaust gas temperature, among cylinders which are controlled targets, is reduced, and a fuel feed amount corresponding to a lower-temperature cylinder of a second predetermined number which is selected to include a lowest exhaust gas temperature, among the cylinders which are the controlled targets, is increased; and a sum of the first predetermined number and the second predetermined number being less than the number of all of the plurality of cylinders so that there is a cylinder whose fuel feed amount is not changed.
    Type: Application
    Filed: September 17, 2009
    Publication date: September 8, 2011
    Applicant: KAWASAKI JUKOGYO KABUSHIKI KAISHA
    Inventors: Tsukasa Imamura, Tomohiko Sugimoto, Tetsuo Tokuoka, Hiroyoshi Ishii