Patents by Inventor Tomohiko Tateyama

Tomohiko Tateyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5362670
    Abstract: Element isolation regions are first formed on a silicon substrate. Active regions other than the isolation regions are formed with an oxide film. Then, a first oxidization prevention layer, a semiconductor layer and a second oxidization prevention layer are formed on the substrate in that order. A resist pattern having a hole in a P-channel MOS transistor formation region is formed. The second oxidization prevention layer in the P-channel MOS transistor formation region is removed and an impurity is ion-implanted using the resist pattern as a mask. After removing the resist pattern, the substrate is thermally treated in the presence of an oxidizer substance to transform an exposed portion of the semiconductor layer into an oxidized semiconductor layer and at the same time to diffuse the implanted impurity in the substrate to thereby form an N-well.
    Type: Grant
    Filed: August 9, 1993
    Date of Patent: November 8, 1994
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuji Iguchi, Shigeki Hayashida, Akio Kawamura, Shinichi Sato, Tomohiko Tateyama