Patents by Inventor Tomohiro Fukuoka

Tomohiro Fukuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8531538
    Abstract: An image processing apparatus includes a decoding processor including a decoder configured to decode encoded data of image data of one frame having a plurality of pixels encoded by a variable length coding method and generating decoded data, and a data transfer unit configured to select decoded data in a target partial region in which a predetermined image processing is to be performed as partial image data out of the decoded data inputted from the decoder and transfer the selected data; and an image processor configured to perform the given image processing on the partial image data selected in the data transfer unit and store the image-processed partial image data in a storage device.
    Type: Grant
    Filed: February 15, 2009
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Motohiro Nakai, Tomohiro Fukuoka
  • Patent number: 8194984
    Abstract: An image processing system is disclosed that includes a buffer unit configured to store a predetermined pixel and peripheral pixels neighboring the predetermined pixel in image data in a first direction and a second direction perpendicular to the first direction; and a first edge-detecting circuit configured to calculate a maximum value and a minimum value of a set of pixels selected from the peripheral pixels that have the same color as the predetermined pixel to calculate a difference value between the maximum value and the minimum value.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: June 5, 2012
    Assignee: Fujitsu Limited
    Inventors: Takeshi Seki, Tomohiro Fukuoka, Kiichiro Iga, Yuji Watarai
  • Patent number: 7983495
    Abstract: An image processing device for use with a storage circuit processes image data for a frame formed by a plurality of pixels. The image processing device includes a first functional macro performing first image processing on the image data, generating first processed image data, and temporarily storing the first processed image in a predetermined region of the storage circuit. A second functional macro performs second image processing following the first image processing. The second functional macro reads the first processed image data from the predetermined region of the storage circuit, performs the second image processing on the first processed image data, and generates second processed image data. A monitor circuit, arranged in the first or second functional macro, monitors a frame processed by the other one of the functional macros and a number of a data line in the frame that is being processed.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: July 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Motohiro Nakai, Tomohiro Fukuoka
  • Patent number: 7978383
    Abstract: A circuit and method for processing an image to correct the pixel value of a sub-pixel included in color data to reduce color differences. The image processing circuit includes a plurality of defect determination circuits respectively corresponding to a plurality of sub-pixels (colors). Each defect determination circuit determines whether or not the corresponding sub-pixel, or first sub-pixel, includes a defect and generates a determination signal. The defect determination circuits provide each of a plurality of correction circuits respectively corresponding to a plurality of sub-pixels (colors) with the determination signals. Each correction circuit generates a corrected value for the corresponding first sub-pixel when at least one of the determination signal is indicative of a defect.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 12, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kouichi Igura, Tomohiro Fukuoka
  • Patent number: 7916964
    Abstract: An image processing apparatus and an image processing method for amplifying an image signal are provided without reducing an image size and without lowering a sense of resolution. An edge-direction detecting arithmetic section (2) detects an edge minimum direction from extracted Bayer data (BAY). An assigning arithmetic section (4) assigns a coefficient in which weighting is applied in the edge minimum direction of the extracted Bayer data (BAY) at a higher distribution ratio than other directions to a spatial filter kernel. In other words, the coefficient of the spatial filter kernel is changed in accordance with the edge minimum direction. A pixel adding arithmetic section (5) performs a sensitization process of extracted Bayer data (BAY). Therefore, it becomes possible to selectively perform a low-pass filtering process in the edge minimum direction.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomohiro Fukuoka
  • Patent number: 7813015
    Abstract: A format conversion circuit converts RGB data to YCbCr data. A one-dimensional compression circuit performs one-dimensional compression process on the YCbCr data to generate one-dimension compression image data and provides the one-dimension compression image data to a base band LSI. The one-dimensional compression circuit includes a memory area that is relatively small but sufficient for holding several bytes of data subject to the compression process.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: October 12, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kiichiro Iga, Tomohiro Fukuoka
  • Patent number: 7800660
    Abstract: An object of the present invention is to provide an image data processing circuit and an image data processing method capable of determining a reference signal level corresponding to black in an image with high precision by suppressing occurrence of line dependency and the like in a dark current component signal included in image data output from a solid state image pickup device. A reference dark current component data holding unit selects a reference line from a solid state image pickup device and holds a dark current component of the reference line as a head line average value. To a subtraction circuit, dark current component data and effective pixel data is sequentially input on the line unit basis. A differential circuit obtains, as a detection value, a change amount with respect to the head line average value, of the dark current component data included in a preceding line. The subtraction circuit subtracts the detection value from the dark current component data and the effective pixel data entered.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: September 21, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kunihiro Ohara, Tomohiro Fukuoka
  • Publication number: 20090207283
    Abstract: An image processing apparatus includes a decoding processor including a decoder configured to decode encoded data of image data of one frame having a plurality of pixels encoded by a variable length coding method and generating decoded data, and a data transfer unit configured to select decoded data in a target partial region in which a predetermined image processing is to be performed as partial image data out of the decoded data inputted from the decoder and transfer the selected data; and an image processor configured to perform the given image processing on the partial image data selected in the data transfer unit and store the image-processed partial image data in a storage device.
    Type: Application
    Filed: February 15, 2009
    Publication date: August 20, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Motohiro NAKAI, Tomohiro Fukuoka
  • Patent number: 7557842
    Abstract: An object is to provide an image processing circuit and an image processing method which can use various technologies for a bayer array CCD even when an RGB independent array CCD is used, and can accommodate for the bayer array CCD. A first matrix acquiring circuit 21G acquires an R signal for each basic matrix, and a first averaging circuit 31G outputs an average value AveCH1 of the R signal. Similarly, a second matrix acquiring circuit 22G acquires a G signal, and a second averaging circuit 32G outputs an average value AveCH2 of the G signal. Further, similarly, a third matrix acquiring circuit 23G acquires a B signal, and a third averaging circuit 33G outputs an average value AveCH3 of the B signal. A data array conversion circuit 40G converts the average values AveCH1 through AveCH3 into a conversion matrix of two pixelsĂ—two pixels in bayer array. The conversion matrix is detected by a detection circuit 70 for bayer array.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: July 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Kunihiro Ohara, Tomohiro Fukuoka
  • Patent number: 7489344
    Abstract: The present invention relates to an image recorder including a selector circuit. Image data output from the image recorder, or output data of an encoder, is format converted in a format conversion circuit, and provided to a selector circuit arranged in a stage either preceding or following a pre-process circuit. The selector circuit selects one of input data from a CCD and input data from the format conversion circuit and provides the selected input data to the pre-process circuit. The output data of the encoder is then fed back. This configures a pseudo imaging system.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: February 10, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Tomohiro Fukuoka, Masaki Okada, Kazuhiko Okada, Hiromi Yokoi, Nobuyuki Hattori
  • Publication number: 20080218782
    Abstract: An image processing system is disclosed that includes a buffer unit configured to store a predetermined pixel and peripheral pixels neighboring the predetermined pixel in image data in a first direction and a second direction perpendicular to the first direction; and a first edge-detecting circuit configured to calculate a maximum value and a minimum value of a set of pixels selected from the peripheral pixels that have the same color as the predetermined pixel to calculate a difference value between the maximum value and the minimum value.
    Type: Application
    Filed: March 4, 2008
    Publication date: September 11, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi SEKI, Tomohiro Fukuoka, Kiichiro Iga, Yuji Watarai
  • Publication number: 20080044088
    Abstract: An image processing device for use with a storage circuit processes image data for a frame formed by a plurality of pixels. The image processing device includes a first functional macro performing first image processing on the image data, generating first processed image data, and temporarily storing the first processed image in a predetermined region of the storage circuit. A second functional macro performs second image processing following the first image processing. The second functional macro reads the first processed image data from the predetermined region of the storage circuit, performs the second image processing on the first processed image data, and generates second processed image data. A monitor circuit, arranged in the first or second functional macro, monitors a frame processed by the other one of the functional macros and a number of a data line in the frame that is being processed.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 21, 2008
    Inventors: Motohiro Nakai, Tomohiro Fukuoka
  • Publication number: 20070285441
    Abstract: An image processing apparatus and an image processing method for amplifying an image signal are provided without reducing an image size and without lowering a sense of resolution. An edge-direction detecting arithmetic section (2) detects an edge minimum direction from extracted Bayer data (BAY). An assigning arithmetic section (4) assigns a coefficient in which weighting is applied in the edge minimum direction of the extracted Bayer data (BAY) at a higher distribution ratio than other directions to a spatial filter kernel. In other words, the coefficient of the spatial filter kernel is changed in accordance with the edge minimum direction. A pixel adding arithmetic section (5) performs a sensitization process of extracted Bayer data (BAY). Therefore, it becomes possible to selectively perform a low-pass filtering process in the edge minimum direction.
    Type: Application
    Filed: April 23, 2007
    Publication date: December 13, 2007
    Inventor: Tomohiro Fukuoka
  • Publication number: 20070268503
    Abstract: An image processing system 1 comprises: a buffer 2 for storing a target pixel oo that is an object of image processing and a group of pixels surrounding the target pixel oo, such that the pixels are aligned in horizontal and vertical directions; a maximum value detector 31 for obtaining a maximum value Bmax from pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; a minimum value detector 32 for obtaining a minimum value Bmin from the pixels of the surrounding pixel group which pixels have the same color as the target pixel oo; and a subtracter 33 for subtracting a result obtained by the minimum value detector 32 from a result obtained by the maximum value detector 31.
    Type: Application
    Filed: May 4, 2007
    Publication date: November 22, 2007
    Inventors: Takeshi Seki, Tomohiro Fukuoka, Kiichiro Iga, Yuji Watarai
  • Publication number: 20070154102
    Abstract: Encoded data obtained by high-efficiency sequential encoding after an orthogonal transformation of image blocks each having a specified number of pixels are used. Preceding image decompression processing is performed on DC encoded data among the encoded data in a DC decompression processing section constituted by a DC decoding section 11A, a DC inverse quantization section 12A and a DC IDCT section 13A, so that an image is displayed. Subsequently, image decompression processing is performed on AC encoded data in addition to the DC encoded data in an AC decompression processing section constituted by an AC decoding section 11B, an AC inverse quantization section 12B and an AC IDCT section 13B, so that an image is displayed. With this procedure, in spite of use of encoded data encoded by a commonly used conventional sequential encoding technique, the same image displaying effect as of the data structure of the progressive encoding technique can be achieved and the displayed image can be sequentially refined.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 5, 2007
    Inventors: Masaki Okada, Tomohiro Fukuoka
  • Publication number: 20070139740
    Abstract: A circuit and method for processing an image to correct the pixel value of a sub-pixel included in color data to reduce color differences. The image processing circuit includes a plurality of defect determination circuits respectively corresponding to a plurality of sub-pixels (colors). Each defect determination circuit determines whether or not the corresponding sub-pixel, or first sub-pixel, includes a defect and generates a determination signal. The defect determination circuits provide each of a plurality of correction circuits respectively corresponding to a plurality of sub-pixels (colors) with the determination signals. Each correction circuit generates a corrected value for the corresponding first sub-pixel when at least one of the determination signal is indicative of a defect.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 21, 2007
    Inventors: Kouichi Igura, Tomohiro Fukuoka
  • Publication number: 20070140581
    Abstract: An image processing circuit for eliminating noise from an image without lowering the actual resolution. The image contains input pixels, which include a processing subject pixel and proximal pixels located proximal to the processing subject pixel. Each input pixel has a pixel value. The image processing circuit includes a spatial filter for generating a filter value for the subject processing pixel based on the pixel values of the input pixels and first filter coefficients. A correction circuit compares the filter value with first and second limit values and corrects the filter value based on the comparison to generate a corrected filter value in a range between the first and second limit values. The image processing circuit eliminates noise from the image by correcting the pixel value of the processing subject pixel based on the corrected filter value.
    Type: Application
    Filed: May 30, 2006
    Publication date: June 21, 2007
    Inventors: Yuji Watarai, Tomohiro Fukuoka
  • Publication number: 20070139539
    Abstract: An object of the present invention is to provide an image data processing circuit and an image data processing method capable of determining a reference signal level corresponding to black in an image with high precision by suppressing occurrence of line dependency and the like in a dark current component signal included in image data output from a solid state image pickup device. A reference dark current component data holding unit selects a reference line from a solid state image pickup device and holds a dark current component of the reference line as a head line average value. To a subtraction circuit, dark current component data and effective pixel data is sequentially input on the line unit basis. A differential circuit obtains, as a detection value, a change amount with respect to the head line average value, of the dark current component data included in a preceding line. The subtraction circuit subtracts the detection value from the dark current component data and the effective pixel data entered.
    Type: Application
    Filed: March 22, 2006
    Publication date: June 21, 2007
    Inventors: Kunihiro Ohara, Tomohiro Fukuoka
  • Publication number: 20070139540
    Abstract: An object is to provide an image processing circuit and an image processing method which can use various technologies for a bayer array CCD even when an RGB independent array CCD is used, and can accommodate for the bayer array CCD. A first matrix acquiring circuit 21G acquires an R signal for each basic matrix, and a first averaging circuit 31G outputs an average value AveCH1 of the R signal. Similarly, a second matrix acquiring circuit 22G acquires a G signal, and a second averaging circuit 32G outputs an average value AveCH2 of the G signal. Further, similarly, a third matrix acquiring circuit 23G acquires a B signal, and a third averaging circuit 33G outputs an average value AveCH3 of the B signal. A data array conversion circuit 40G converts the average values AveCH1 through AveCH3 into a conversion matrix of two pixelsĂ—two pixels in bayer array. The conversion matrix is detected by a detection circuit 70 for bayer array.
    Type: Application
    Filed: March 17, 2006
    Publication date: June 21, 2007
    Inventors: Kunihiro Ohara, Tomohiro Fukuoka
  • Publication number: 20060244992
    Abstract: A format conversion circuit converts RGB data to YCbCr data. A one-dimensional compression circuit performs one-dimensional compression process on the YCbCr data to generate one-dimension compression image data and provides the one-dimension compression image data to a base band LSI. The one-dimensional compression circuit includes a memory area that is relatively small but sufficient for holding several bytes of data subject to the compression process.
    Type: Application
    Filed: October 4, 2005
    Publication date: November 2, 2006
    Inventors: Kiichiro Iga, Tomohiro Fukuoka