Abstract: A sanitary washing device includes: a nozzle configured to wash a local region of a human body; a tank configured to accommodate a sterilizing agent, a sterilizing component of which is dissolved into liquid, and to store supplied liquid therein; a nozzle washing unit configured to wash the nozzle using liquid supplied from the tank; and a buffering unit disposed between the sterilizing agent and an inner wall of the tank inside the tank and having liquid permeability.

Abstract: A sanitary washing device includes: a nozzle configured to wash a local region of a human body; a tank configured to accommodate a sterilizing agent, a sterilizing component of which is dissolved into liquid, and to store supplied liquid therein; a nozzle washing unit configured to wash the nozzle using liquid supplied from the tank; and a buffering unit disposed between the sterilizing agent and an inner wall of the tank inside the tank and having liquid permeability.

Abstract: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the semiconductor substrate, and a node electrode formed above the first diffusion layer, and coupled thereto. The first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the semiconductor substrate, and a node electrode formed above the first diffusion layer, and coupled thereto. The first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode.

Abstract: A non-volatile semiconductor memory device includes a substrate, a first insulating film formed on the substrate, a second insulating film formed on the first insulating film, a plurality of granular dots formed in the second insulating film adjacent to the first insulating film as a floating gate, and a control gate formed on the second insulating film. The second insulating film is a high dielectric constant film made of oxide whose dielectric constant is higher than that of the first insulating film and whose heat of formation is higher than that of silicon oxide.

Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film. The first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines. The second diffusion region is connected to a program and erase bit line.

Abstract: A non-volatile semiconductor memory device includes a substrate, a first insulating film formed on the substrate, a second insulating film formed on the first insulating film, a plurality of granular dots formed in the second insulating film adjacent to the first insulating film as a floating gate, and a control gate formed on the second insulating film. The second insulating film is a high dielectric constant film made of oxide whose dielectric constant is higher than that of the first insulating film and whose heat of formation is higher than that of silicon oxide.

Abstract: A semiconductor memory device includes a first insulating film provided on a semiconductor substrate between first and second diffusion regions, a first gate electrode provided on the first insulating film, a second insulating film provided on the semiconductor substrate between the second diffusion region and a third diffusion region, and a second gate electrode provided on the second insulating film are included, wherein the first and second diffusion regions, first insulating film, and first gate electrode constitute a first memory cell, while the second and third diffusion regions, second insulating film, and second gate electrode constitute a second memory cell. The first and second gate electrodes are connected in common to form a word line electrode. The first and third diffusion regions are connected to first and second read bit lines disposed on a layer overlying the semiconductor substrate.

Abstract: An insulating layer is selectively grown on the major surface of a first silicon wafer, and is partially etched away so as to be retracted below the major surface; after the retraction of the insulating layer, the first silicon wafer is bonded to a second silicon wafer, and the major surface of the first silicon wafer is strongly adhered to the major surface of the second silicon wafer, so that the first silicon wafer is hardly separated from the second silicon wafer.

Abstract: An insulating layer is selectively grown on the major surface of a first silicon wafer, and is partially etched away so as to be retracted below the major surface; after the retraction of the insulating layer, the first silicon wafer is bonded to a second silicon wafer, and the major surface of the first silicon wafer is strongly adhered to the major surface of the second silicon wafer, so that the first silicon wafer is hardly separated from the second silicon wafer.

Abstract: A semiconductor wafer having an SOI (Silicon-On-Insulator) structure and capable of being accurately aligned without undesirable contrast appearing in an infrared transmission image. The wafer is implemented as a laminate SOI wafer including an SOI layer. An aligning oxide film pattern and an oxide film pattern are buried in the SOI layer. The aligning oxide film pattern and oxide film pattern are respectively aligned with an aligning mask pattern and a mask pattern provided on a masking quartz wafer. In this condition, the laminate wafer is subjected to preselected processing. One of opposite major surfaces of the SOI wafer facing the quartz wafer is smoothed over its regions containing at least the aligning oxide film pattern and through which infrared rays are to be transmitted with respect to photoresist. The other major surface is smoothed over the above regions by having a polycrystal silicon film thereof removed.

Abstract: A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.

Abstract: Two wafers of single-crystal silicon are used to produce a bonded substrate having a silicon-on-insulator (SOI) structure. In a principal surface of a first wafer, a number of first insulator film patterns of equal thickness art formed for isolation of semiconductor devices to be fabricated on the bonded substrate. Simultaneously, at least to second insulator film patterns having the same thickniess as the first insulator film patterns are formed in the same surface of the first wafer for optical measurement of the thickness of an active layer of in the bonded substrate. Then the first wafer is bonded to a second wafer to obtain a bonded substrate in which the insulator film patterns are buried adjacent to the interface between the two silicon wafers. To form an active layer having a desired thickness above the buried insulator film patterns, the thickness of the first wafer is reduced by mechanical grinding and chemical-mechanical polishing.

Abstract: The present invention provides a silicon-on-insulator substrate comprising a first silicon substrate, a second silicon substrate bonded to the first silicon substrate, a plurality of insulation film patterns formed on a plurality of first type regions of an interface between the first and second silicon substrate, so that the first and second silicon substrates on the plurality of first type regions are indirectly bonded through the plurality of insulation film patterns while the first and second silicon substrates on a plurality of second type regions are directly bonded to each other, wherein each of the plurality of first type regions is bounded on all sides by the plurality of second type regions while each of the plurality of second type regions is bounded on all sides by the plurality of first type regions.

Abstract: Disclosed herein is a composite SOI substrate which allows, by use of a conventional visible light aligner, high-precision alignment of insulator film patterns buried in an SOI substrate and patterns which are to be formed on the SOI layer located above it. The composite SOI substrate is fabricated by forming alignment oxide film patterns I a on the periphery of a main surface of a first silicon substrate 10 which also has buried oxide film patterns formed thereon; preparing a second silicon substrate having preferably V-shaped notch sections 9 on its periphery to expose the alignment patterns provided on the first silicon substrate; bonding the second silicon substrate to the main surface side of the first silicon substrate 10 while exposing the alignment oxide film patterns 1a; and then thinning the second silicon substrate to form an SOI layer 20a.

Abstract: A semiconductor device includes a groove formed in a surface of a first semiconductor substrate of one conductivity type in order to partition and isolate first and second device regions. A first insulating film on the first semiconductor substrate of the first device region also contacts the groove. A second insulating film covers an inner wall of the groove. The first insulating film is thicker than the second film in order to increase the breakdown voltage and facilitate carrying a higher current. This thickness relationship also aids manufacturing.

Abstract: After forming a groove on one surface of a single-crystalline silicon layer, a silicon oxide layer is formed. Also, a polycrystalline silicon layer is formed on the silicon oxide layer to cover the groove. Subsequently, by a buffer layer of polycrystalline silicon is deposited over the polycrystalline silicon layer to form a smooth surface. Thereafter, a silicon oxide layer is formed on a separately prepared supporting substrate. After laminating both substrates by mating the buffer layer and the silicon oxide layer, annealing is performed. By this, voids which might otherwise be generated at the junction interface in the dielectric isolation substrate can be eliminated.

Abstract: A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.