Abstract: A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.

Abstract: A ventilation structure of a shoe sole of the present invention includes the shoe sole 1 formed with a through hole 5 vertically passing therethrough. The through hole 5 is fitted with a ventilation part 6. The ventilation part 6 comprises a flange portion 60 and the projection 61. The flange portion 60 engages the upper surface 2a of the shoe sole 1 so that the ventilation part 6 does not drop off the through hole 5. The projection 61 extends into the through hole 5. The projection 61 is provided with a vent hole 62 vertically passing therethrough for the passage of air.

Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.

Abstract: A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.

Abstract: A nonslip member in which a large number of nonslip convexes are fixed to an upper surface of a base fabric performing an anchoring action, and the nonslip convexes are made of rubber.

Abstract: A nonslip member in which a large number of nonslip convexes are fixed to an upper surface of a base fabric performing an anchoring action, and the nonslip convexes are made of rubber. By engaging a male mold and a female mold with each other, a large number of small pieces coincident to a shape of through holes of the female mold are punched out from a plate-like material. By pressurizing and heating each small piece between a punching convex and a mounting base while engaging the male mold and the female mold with each other, the small piece is bridged and fixed to the base fabric to serve as a nonslip convex.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: A phase locked loop circuit that rapidly synchronizes an internal synchronizing signal with the reference signal includes a phase detector detecting the difference between the signals, a current generator, a charge pump controlled by the phase detector generating voltage by converting current from the current generator into a control voltage, a lock detector detecting whether the phase difference between the signals is within a predetermined range, a loop filter with variable capacitance that is charged and discharged by the control voltage from the charge pump and which changes capacitance is response to lock and unlock signals from the lock detector, and a voltage controlled oscillator converting the control voltage into the internal synchronizing signal. When the phase difference between the signals is within the predetermined range, the lock detector outputs a "lock" signal to the loop filter, and the capacitance of the filter is set to be large.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: A multiple-valued memory is capable of storing analog quantities which are distinguishable in a plurality of levels, and includes a plurality of memory cells capable of storing n-valued logic values depending on the stored analog quantities, where n is three or greater. The multiple-valued memory is constructed such that correspondences between the analog quantities to be stored by the memory cells and the logic values to be stored in the memory cells are set so that a Hamming distance between two logic values respectively corresponding to an analog quantity having an i-th level and an analog quantity having a (i+1)-th level is one.

Abstract: A derived database processing system in a database processing device comprises a plurality of independent databases which can provide a plurality of users with a group of data to be shared for a common purpose. The derived database processing system comprises a dictionary for managing database logical definition information and database storage information in a secondary memory, a derived database registering unit for determining a definition frame of a new name without violating a definition frame of a name used in a schema definition which defines data in a database, a dictionary information manipulating means for referring to said dictionary when the manipulation target is a derived database, then selecting necessary components of said database, and a database processing procedure generating unit, in a binding process to optimize access routing in a database.

Abstract: A derived database processing system in a database processing device comprises a plurality of independent databases which can provide a plurality of users with a group of data to be shared for a common purpose. The derived database processing system comprises a dictionary for managing database logical definition information and database storage information in a secondary memory, a derived database registering unit for determining a definition frame of a new name without violating a definition frame of a name used in a schema definition which defines data in a database, a dictionary information manipulating means for referring to said dictionary when the manipulation target is a derived database, then selecting necessary components of said database, and a database processing procedure generating unit, in a binding process to optimize access routing in a database.

Abstract: A method of developing a self-describing database management system comprises the steps of holding definition data of a database management system to be developed as data on a database and creating a database management system to be developed by the use of an existing database management system. The database management system to be developed comprises a data definition processing execution program and a bind processing execution program. These two programs include a process to permit access to definition data which form database, and are executed based on the definition data on the database.

Abstract: Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to rearrange the memory area.

Abstract: A database generic composite structure processing system stores data expressed by a logical structure and generates an access schedule in response to an query. The system comprises a generic composite structure element for storing definition information for associating a partial data comprising a table or a partial table expressed by a logical structure with a composite structure of a database in an independent structure in physical media, and for storing definition information for storing data and an optimizing process element for generating, according to the generic composite structure defined by said generic composite structure means, an executable module which is a concrete result of an access schedule in response to an query.

Abstract: A method of detecting and correcting an error which may be contained in digital data includes steps of (a) arranging the digital data in a plurality of dimensions equal to or higher than a fourth dimension so that arranged data is obtained for each of the plurality of dimensions, (b) producing error detection and correction data for the arranged data obtained for each of the plurality of dimensions, and (c) detecting and correcting an error which may be contained in the digital data by using the error detection and correction data.

Abstract: A log data management system is used with a database processing system. The log data management system has a plurality of database update units coupled to a database through a common bus. Each of the database update units updates a resource of the database and records log data as an update record. The database update unit writes log data of the resource of the database in a local memory in order of update time of the resource. After the resource has been updated, the database update unit transfers the log data written in the local memory to the common memory. At this time, since the database update unit does not free the resource until the log data is non-volatilized in the common memory, log data are successively stored in the common memory in order of the update time of the resource. When a failure takes place in a resource of the database, log data stored in the common memory are referred to and thereby the resource is quickly closed and recovered.

Abstract: In a data base processing system using a multiprocessor system, the data base processing system includes: a storage unit provided in the shared memory for storing data base management information representing either an object of a shared processing operation or an object of a local processing operation for every resource; an access management unit provided in each of the processor modules for performing an access control for an access request to the data base under either the shared processing operation or the local processing operation in accordance with the data base management information, the shared processing operation being symmetrically performed, and the local processing operation being asymmetrically performed in each processor module; and a control unit provided in the processor module for controlling the shared/local conversion in such a way that: an access state of the resource is managed for every resource; when a frequency of the access is unevenly distributed to a particular processor module, t

Abstract: A database processing system using a multi-processor including a plurality of processor modules each having a local memory connected to an external shared memory. The database processing system includes a composite structure definition control part for defining an administrative processor module for controlling an access to a composite structure of a database which has a storage structure independent of a logical structure; and a maintenance/selection control part in an optimum control processor for providing a function of access-controlling a shared process and a local process when an access request arises for a database composite structure, and for dynamically switching the access control process for the composite structure according to the access frequency notified by each processor module.