Patents by Inventor Tomohiro Hirai
Tomohiro Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969975Abstract: A protective cover member includes a laminate including: a protective membrane having a shape configured to cover an opening when the protective cover member is placed on the face of an object; a substrate film joined to the protective membrane; and a first adhesive layer configured to fix the protective cover member to the face, wherein an outer peripheral surface of the protective cover member has a step in a laminating direction of the laminate, a first portion of the protective cover member protrudes at the step more outward than a second portion of the protective cover member does when the protective cover member is placed on the face, the first portion being positioned farther from the face than the step, the second portion being positioned closer to the face than the step, and the protective membrane and the substrate film are positioned in the first portion.Type: GrantFiled: July 3, 2020Date of Patent: April 30, 2024Assignee: NITTO DENKO CORPORATIONInventors: Yuichi Abe, Tomohiro Kontani, Takeo Inoue, Bunta Hirai
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Patent number: 11933022Abstract: A tractor includes a working motor, a work machine including a roller configured to rotate by an output from the working motor, a support mechanism configured to support the work machine such that a working posture and a retracting posture are achievable, and a control device. The control device executes: an adherence amount acquisition process of acquiring an estimated adherence amount as an estimated value for the amount of mud attached to the roller; and a mud removal process of, when the estimated adherence amount is equal to or more than a determination adherence amount, removing the mud from the roller by driving the working motor in a state where the work machine takes the retracting posture.Type: GrantFiled: February 25, 2022Date of Patent: March 19, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yuki Sugo, Masaki Numakura, Makoto Hirai, Taiga Higuchi, Tomohiro Sato, Hiroyuki Azuma
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Patent number: 11888020Abstract: The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type. Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.Type: GrantFiled: February 7, 2020Date of Patent: January 30, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Chihiro Tomita, Shintaro Okamoto, Tomohiro Hirai
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Patent number: 11837668Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.Type: GrantFiled: September 30, 2019Date of Patent: December 5, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Chihiro Tomita, Tomohiro Hirai, Shintaro Okamoto, Kentaro Eda, Takashi Watanabe, Kazuki Yamaguchi, Norikazu Kasahara, Kohei Suzuki
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Publication number: 20220384561Abstract: A resistance element includes a resistive film, in which the resistive film is adjacent to a protrusion formed on a surface of a semiconductor substrate, the protrusion including a step traversed by the resistive film.Type: ApplicationFiled: August 7, 2020Publication date: December 1, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Chihiro TOMITA, Tomohiro HIRAI
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Publication number: 20220130948Abstract: The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type. Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.Type: ApplicationFiled: February 7, 2020Publication date: April 28, 2022Inventors: CHIHIRO TOMITA, SHINTARO OKAMOTO, TOMOHIRO HIRAI
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Publication number: 20220052208Abstract: The capacity of a MOS capacitor is increased. A semiconductor element includes a first semiconductor region, an insulation film, a gate electrode, and a second semiconductor region. The first semiconductor region is arranged on a semiconductor substrate and has a recess on the surface. The insulation film is arranged adjacent to the surface of the first semiconductor region. The gate electrode is arranged adjacent to the insulation film and constitutes a MOS capacitor with the first semiconductor region. The second semiconductor region is arranged adjacent to the first semiconductor region on the semiconductor substrate, formed in the same conductive type as the first semiconductor region, and supplies a carrier to the first semiconductor region when the MOS capacitor is charged and discharged.Type: ApplicationFiled: September 30, 2019Publication date: February 17, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Chihiro TOMITA, Tomohiro HIRAI, Shintaro OKAMOTO, Kentaro EDA, Takashi WATANABE, Kazuki YAMAGUCHI, Norikazu KASAHARA, Kohei SUZUKI
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Patent number: 10256100Abstract: The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film is formed above a gate electrode above a substrate with an interlayer insulation film interposed and a source electrode coupled to a barrier layer on one side of the gate electrode and a drain electrode coupled to the barrier layer on the other side of the gate electrode are formed by etching the electrically-conductive film. On this occasion, the source electrode is etched so as to have a shape extending beyond above the gate electrode to the side of the drain electrode and having a gap (opening) above the gate electrode. Successively, hydrogen annealing is applied to the substrate. In this way, by forming the gap at a source field plate section of the source electrode, it is possible to efficiently supply hydrogen in the region where a channel is formed in the hydrogen annealing process.Type: GrantFiled: December 15, 2015Date of Patent: April 9, 2019Assignee: Renesas Electronics CorporationInventors: Tomohiro Hirai, Hiroshi Kawaguchi
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Publication number: 20160260615Abstract: The present invention makes it possible to improve the characteristic of a semiconductor device using a nitride semiconductor. An electrically-conductive film is formed above a gate electrode above a substrate with an interlayer insulation film interposed and a source electrode coupled to a barrier layer on one side of the gate electrode and a drain electrode coupled to the barrier layer on the other side of the gate electrode are formed by etching the electrically-conductive film. On this occasion, the source electrode is etched so as to have a shape extending beyond above the gate electrode to the side of the drain electrode and having a gap (opening) above the gate electrode. Successively, hydrogen annealing is applied to the substrate. In this way, by forming the gap at a source field plate section of the source electrode, it is possible to efficiently supply hydrogen in the region where a channel is formed in the hydrogen annealing process.Type: ApplicationFiled: December 15, 2015Publication date: September 8, 2016Applicant: Renesas Electronics CorporationInventors: Tomohiro HIRAI, Hiroshi KAWAGUCHI
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Publication number: 20160027872Abstract: A semiconductor device, includes a substrate, a source structure and a drain structure formed on the substrate. At least one interconnect structure interconnects the source structure and the drain structure and serves as a channel therebetween. A gate structure is formed over the at least one interconnect structure to provide a control of a conductivity of carriers in the channel. Each of the interconnect structures include a center core serving as a backbias electrode for the channel.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Tomohiro HIRAI, Toshiharu NAGUMO
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Publication number: 20160020312Abstract: A method of fabricating a semiconductor device with a reduced leakage method includes forming a channel structure on a substrate, the channel structure having a non-uniform composition, in a cross-sectional view, that comprises a core region and a peripheral region. An etch rate of the core region differs from an etch rate of the peripheral region. A source structure connected to one end of the channel structure is formed, and a drain structure connected to the other end of the channel structure is formed. At least a portion of the core region is electively etched and a gate structure to cover at least a portion of a surface of the channel structure, is formed, the gate structure comprising a film of insulation material and a gate electrode.Type: ApplicationFiled: September 30, 2015Publication date: January 21, 2016Inventors: Tomohiro HIRAI, Shogo Mochizuki, Toshiharu Nagumo
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Patent number: 9196715Abstract: A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode. A source structure is connected to one end of the channel structure, and a drain structure is connected to the other end of the channel structure. The channel structure has a non-uniform composition, in a cross-sectional view, that provides a reduction of a leakage current of the semiconductor device relative to a leakage current that would result from a uniform composition.Type: GrantFiled: December 19, 2013Date of Patent: November 24, 2015Assignee: Renesas Electronics CorporationInventors: Tomohiro Hirai, Shogo Mochizuki, Toshiharu Nagumo
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Patent number: 9190505Abstract: A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween. A gate structure is formed over said at least one nanowire structure to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel.Type: GrantFiled: December 19, 2013Date of Patent: November 17, 2015Assignee: Renesas Electronics CorporationInventors: Tomohiro Hirai, Toshiharu Nagumo
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Publication number: 20140183451Abstract: A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode. A source structure is connected to one end of the channel structure, and a drain structure is connected to the other end of the channel structure.Type: ApplicationFiled: December 19, 2013Publication date: July 3, 2014Applicant: Renesas Electronics CorporationInventors: Tomohiro HIRAI, Shogo Mochizuki, Toshiharu Nagumo
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Publication number: 20140183452Abstract: A semiconductor device includes a substrate and a source structure and a drain structure formed on the substrate. At least one nanowire structure interconnects the source structure and drain structure and serves as a channel therebetween. A gate structure is formed over said at least one nanowire structure to provide a control of a conductivity of carriers in the channel, and the nanowire structure includes a center core serving as a backbias electrode for the channel.Type: ApplicationFiled: December 19, 2013Publication date: July 3, 2014Applicant: Renesas Electronics CorporationInventors: Tomohiro HIRAI, Toshiharu NAGUMO
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Patent number: 8390050Abstract: A semiconductor device has a first-conductivity-type-channel MOSFET formed on a semiconductor substrate, wherein the first-conductivity-type-channel MOSFET is typically a P-channel MOSFET, and is composed of a gate insulating film and a gate electrode provided over the semiconductor substrate, the gate electrode contains a metal gate electrode provided over the gate insulating film, a metal oxide film provided over the metal gate electrode, and another metal gate electrode provided over metal oxide film.Type: GrantFiled: June 25, 2010Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventor: Tomohiro Hirai
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Publication number: 20110024845Abstract: A semiconductor device has a first-conductivity-type-channel MOSFET formed on a semiconductor substrate, wherein the first-conductivity-type-channel MOSFET is typically a P-channel MOSFET, and is composed of a gate insulating film and a gate electrode provided over the semiconductor substrate, the gate electrode contains a metal gate electrode provided over the gate insulating film, a metal oxide film provided over the metal gate electrode, and another metal gate electrode provided over metal oxide film.Type: ApplicationFiled: June 25, 2010Publication date: February 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tomohiro HIRAI