Abstract: A fixed-length delay generation circuit comprises a first variable delay circuit (VDC), a clock generation circuit, a VDC group including one or more second VDCs, and a delay controller. The clock signal is input to a second VDC disposed at the initial stage in the VDC group. The delay controller outputs a signal by which delay amount in the first and second VDCs are made smaller when a difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is greater than a predetermined value. The delay controller outputs a signal by which delay amount in the first and second VDCs are made larger when the difference between phases of a delay clock signal output from the VDC group and of the clock signal generated by the clock generation circuit is smaller than such value.

Abstract: A power window motor drive apparatus, which, in the event of data error of the external command data, from the driver's seat limits the generation of drive signals for the power window motor that are based on the internal command data internally generated by the operation of the window switch and on the external command data received from outside through the communications line. An external command data reference inhibit means is provided to inhibit only the generation of the drive signals based on the external command data.