Patents by Inventor Tomohiro Kadoya
Tomohiro Kadoya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10468347Abstract: Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.Type: GrantFiled: March 17, 2015Date of Patent: November 5, 2019Assignee: Micron Technology, Inc.Inventor: Tomohiro Kadoya
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Publication number: 20160071843Abstract: A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.Type: ApplicationFiled: November 17, 2015Publication date: March 10, 2016Applicant: PS4 Luxco S.a.r.l.Inventor: Tomohiro Kadoya
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Patent number: 9209192Abstract: A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.Type: GrantFiled: December 30, 2010Date of Patent: December 8, 2015Assignee: PS4 Luxco S.a.r.l.Inventor: Tomohiro Kadoya
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Publication number: 20150294934Abstract: Disclosed herein is a device that includes a substrate, a contact plug disposed on the substrate, an interlayer dielectric over the substrate to define the contact plug, a titanium silicide extending continuously from an upper portion of the contact plug to over the interlayer dielectric, a conductive material disposed over the titanium silicide.Type: ApplicationFiled: March 17, 2015Publication date: October 15, 2015Inventor: Tomohiro Kadoya
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Patent number: 8956961Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.Type: GrantFiled: March 9, 2012Date of Patent: February 17, 2015Assignee: Rexchip Electronics CorporationInventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
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Publication number: 20130234230Abstract: A semiconductor device includes: a substrate having a base and an array of semiconductor pillars extending from the base, the substrate being formed with a plurality of trenches, each of which extends into the base and has two opposing trench side walls; a first insulative liner layer formed on each of the trench side walls of each of the trenches and divided into upper and lower segments by a gap that leaves a bit-forming surface of each of the trench side walls uncovered by the first insulative liner layer; and a plurality of buried bit lines, each of which extends into the base from the bit-forming surface of a respective one of the trench side walls of each of the trenches.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Inventors: Kazuaki Takesako, Wen-Kuei Hsu, Yoshinori Tanaka, Yukihiro Nagai, Chih-Wei Hsiung, Hirotake Fujita, Tomohiro Kadoya, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang
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Publication number: 20130193511Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.Type: ApplicationFiled: January 26, 2012Publication date: August 1, 2013Inventors: Hsuan-Yu FANG, Wei-Chih Liu, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang, Kazuaki Takesako, Tomohiro Kadoya, Wen Kuei Hsu, Hirotake Fujita, Yukihiro Nagai, Chih-Wei Hsiung, Yoshinori Tanaka
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Publication number: 20130157454Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Inventors: Wei-Che CHANG, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
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Patent number: 8461056Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.Type: GrantFiled: December 15, 2011Date of Patent: June 11, 2013Assignee: Rexchip Electronics CorporationInventors: Wei-Che Chang, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
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Patent number: 8399916Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.Type: GrantFiled: March 5, 2012Date of Patent: March 19, 2013Assignee: Elpida Memory, Inc.Inventor: Tomohiro Kadoya
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Publication number: 20120161283Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.Type: ApplicationFiled: March 5, 2012Publication date: June 28, 2012Inventor: Tomohiro KADOYA
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Patent number: 8134398Abstract: A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.Type: GrantFiled: November 15, 2010Date of Patent: March 13, 2012Assignee: Elpida Memory, Inc.Inventor: Tomohiro Kadoya
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Patent number: 8129769Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.Type: GrantFiled: December 15, 2009Date of Patent: March 6, 2012Assignee: Elpida Memory, Inc.Inventor: Tomohiro Kadoya
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Publication number: 20110169062Abstract: A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion.Type: ApplicationFiled: December 30, 2010Publication date: July 14, 2011Applicant: Elpida Memory, Inc.Inventor: Tomohiro Kadoya
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Publication number: 20110104862Abstract: A method of forming a semiconductor device includes the following processes. A first semiconductor structure is formed, which extends upwardly in a direction perpendicular to a main surface from a surface of a semiconductor substrate. A first insulating film is formed which extends on a surface of the first semiconductor structure. A gate electrode is formed which extends on the first insulating film. The gate electrode has a top surface which is lower than a top surface of the first semiconductor structure. A liner film is formed, which may include, but is not limited to, first and second liner portions. The first liner portion covers the gate electrode. The second liner portion extends upwardly from the top surface of the gate electrode. The liner film includes nitrogen and oxygen.Type: ApplicationFiled: November 2, 2010Publication date: May 5, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Tomohiro KADOYA
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Publication number: 20110057260Abstract: A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.Type: ApplicationFiled: November 15, 2010Publication date: March 10, 2011Applicant: ELPIDA MEMORY, INC.Inventor: TOMOHIRO KADOYA
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Patent number: 7859038Abstract: A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.Type: GrantFiled: December 16, 2008Date of Patent: December 28, 2010Assignee: Elpida Memory, Inc.Inventor: Tomohiro Kadoya
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Publication number: 20100148236Abstract: A semiconductor device having a 6F2 memory cell whose size is defined by a numerical value of a design rule F, wherein: lower electrodes of capacitors included in the memory cell are supported by a support film; the support film is formed as a pattern combining a first support pattern (14x) linearly extending in a first direction and a second support pattern (14y) linearly extending in a second direction that crosses to the first direction; the support film is arranged such that the intervals of the first and second support patterns are both equal to or greater than 1.5F; and the interval of one of the first and second support patterns is greater than the interval of the other one of the first and second support patterns.Type: ApplicationFiled: December 15, 2009Publication date: June 17, 2010Inventor: Tomohiro KADOYA
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Publication number: 20100109062Abstract: A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction.Type: ApplicationFiled: December 16, 2008Publication date: May 6, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Tomohiro KADOYA
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Publication number: 20100072542Abstract: Modification of an SOD film is promoted in a hot oxidizing atmosphere. Elements under a liner film and a semiconductor substrate are prevented from being damaged by oxidation. A semiconductor device includes a recess portion, a first liner film and a second liner film sequentially formed on inner wall side surfaces of the recess portion, the second liner film containing an oxygen atom, and an insulating region filled in the recess portion. The first liner film has a higher oxidation resistance than the second liner film.Type: ApplicationFiled: September 14, 2009Publication date: March 25, 2010Inventors: Tomohiro Kadoya, Kazuma Shimamoto