Abstract: In a converter circuit of an electric power conversion device, an adjustment portion divides a voltage of a battery input to a semiconductor module, by a first capacity element and a second capacity element that are connected in series to each other. Then, a middle point between the first capacity element and the second capacity element is connected to a cooler to fix a potential thereof. The electric power conversion device can ensure that a waveform of a surge voltage that is generated on a creepage surface between a lead frame terminal and the cooler has a negative voltage range (a range where an offset voltage is applied).

Abstract: In a converter circuit of an electric power conversion device, an adjustment portion divides a voltage of a battery input to a semiconductor module, by a first capacity element and a second capacity element that are connected in series to each other. Then, a middle point between the first capacity element and the second capacity element is connected to a cooler to fix a potential thereof. The electric power conversion device can ensure that a waveform of a surge voltage that is generated on a creepage surface between a lead frame terminal and the cooler has a negative voltage range (a range where an offset voltage is applied).

Abstract: First, there are prepared a semiconductor chip with a group of solder bumps disposed on and joined to a surface thereof in a predetermined pattern, and a multilayer plate including a second layer as an electrically conductive layer and first and third layers disposed on respective opposite surfaces of the second layer and comprising metal layers of one metal. Then, the first layer and the third layer of the multilayer plate are etched in a predetermined pattern to form a first group of posts and a second group of posts which have a pattern identical to the pattern of the group of solder bumps. Then, semiconductor chip is positioned to hold the solder bumps in contact with the posts of the first group, and the solder bumps are melted to join the solder bumps to the posts of the first group. Thereafter, the second layer is cut between the posts of the first and second groups, producing separate multilayer posts.

Abstract: First, there are prepared a semiconductor chip with a group of solder bumps disposed on and joined to a surface thereof in a predetermined pattern, and a multilayer plate including a second layer as an electrically conductive layer and first and third layers disposed on respective opposite surfaces of the second layer and comprising metal layers of one metal. Then, the first layer and the third layer of the multilayer plate are etched in a predetermined pattern to form a first group of posts and a second group of posts which have a pattern identical to the pattern of the group of solder bumps. Then, semiconductor chip is positioned to hold the solder bumps in contact with the posts of the first group, and the solder bumps are melted to join the solder bumps to the posts of the first group. Thereafter, the second layer is cut between the posts of the first and second groups, producing separate multilayer posts.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate; at least a pad electrode provided over the semiconductor substrate; a passivation film provided over the semiconductor substrate; an insulative resin stress buffer layer provided over the at least pad electrode and the passivation film, the insulative resin stress buffer layer having at least an opening positioned over at least a part of the at least pad electrode; and at least a land portion provided over the insulative resin stress buffer layer and also electrically connected to the at least pad electrode, and a top surface of the at least land portion being electrically connected to at least a bump which is positioned over the at least land portion, wherein the at least land portion and the passivation film are isolated from each other by the insulative resin stress buffer layer.

Abstract: First, there are prepared a semiconductor chip with a group of solder bumps disposed on and joined to a surface thereof in a predetermined pattern, and a multilayer plate including a second layer as an electrically conductive layer and first and third layers disposed on respective opposite surfaces of the second layer and comprising metal layers of one metal. Then, the first layer and the third layer of the multilayer plate are etched in a predetermined pattern to form a first group of posts and a second group of posts which have a pattern identical to the pattern of the group of solder bumps. Then, semiconductor chip is positioned to hold the solder bumps in contact with the posts of the first group, and the solder bumps are melted to join the solder bumps to the posts of the first group. Thereafter, the second layer is cut between the posts of the first and second groups, producing separate multilayer posts.

Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate; at least a pad electrode provided over the semiconductor substrate; a passivation film provided over the semiconductor substrate; an insulative resin stress buffer layer provided over the at least pad electrode and the passivation film, the insulative resin stress buffer layer having at least an opening positioned over at least a part of the at least pad electrode; and at least a land portion provided over the insulative resin stress buffer layer and also electrically connected to the at least pad electrode, and a top surface of the at least land portion being electrically connected to at least a bump which is positioned over the at least land portion, wherein the at least land portion and the passivation film are isolated from each other by the insulative resin stress buffer layer.