Abstract: Microelectronic devices may include first bond pads located proximate to, and distributed along, a first side of the microelectronic device. Other bond pads may be located proximate to, and distributed along, another side of the microelectronic device perpendicular to the first side. A first pitch of the first bond pads may be greater than another pitch of the other bond pads. When microelectronic devices are placed side by side, the bond pads on sides of the microelectronic devices proximate to one another may be interposed between one another in the direction parallel to the first shortest distance between adjacent first bond pads.

Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

Abstract: A semiconductor device may include a bond pad/probe pad pair that includes a bond pad and a probe pad positioned to be adjacent to each other to form an L shape. The device may also include a through-silicon via (TSV) pad positioned to be at least partially or entirely inside the recess area of the L shape. The bond pad and the probe pad may each have an opening, and at least a portion of the opening of the bond pad may extend into a portion of the opening of the probe pad. The arrangement of the bond pad, the probe pad and the TSV may be implemented in a wafer-on-wafer (WOW) that includes multiple stacked wafers. A method of fabricating the TSV may include etching the stacked wafers to form a TSV opening that extends through the multiple wafers, and filling the TSV opening with conductive material.

Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

Abstract: A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Abstract: A design method for a semiconductor integrated circuit includes a first step (S13) of grouping pins that configure a same net into a plurality of groups; a second step (S14) of defining sub-trunk wirings mutually connecting the pins that belong to a same group; a third step (S16) of defining a main trunk wiring substantially parallel to the sub-trunk wirings; and a fourth step (S17) of defining a lead-in wiring connecting at least the main trunk wiring and the sub-trunk wirings. Thus, a plurality of pins are grouped, and the groups are mutually connected by the sub-trunk wirings, making it possible to decrease the number of the lead-in wirings. Thereby, even when the number of nets is large relative to the area of a layout region, a probability of occurrence of nets where automatic wiring is impossible can be greatly reduced.

Abstract: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Abstract: The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information.

Abstract: A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can be placed so as to share part of its region with a standard cell placed adjacent to that standard cell. On the basis of the determination result, when placing a standard cell, a standard cell to be placed adjacent to that standard cell is placed so as to share part of its region, thereby making it possible to reduce the placement area.

Abstract: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Abstract: A design method for a semiconductor integrated circuit includes a first step (S13) of grouping pins that configure a same net into a plurality of groups; a second step (S14) of defining sub-trunk wirings mutually connecting the pins that belong to a same group; a third step (S16) of defining a main trunk wiring substantially parallel to the sub-trunk wirings; and a fourth step (S17) of defining a lead-in wiring connecting at least the main trunk wiring and the sub-trunk wirings. Thus, a plurality of pins are grouped, and the groups are mutually connected by the sub-trunk wirings, making it possible to decrease the number of the lead-in wirings. Thereby, even when the number of nets is large relative to the area of a layout region, a probability of occurrence of nets where automatic wiring is impossible can be greatly reduced.

Abstract: A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can be placed so as to share part of its region with a standard cell placed adjacent to that standard cell. On the basis of the determination result, when placing a standard cell, a standard cell to be placed adjacent to that standard cell is placed so as to share part of its region, thereby making it possible to reduce the placement area.

Abstract: The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.