Patents by Inventor Tomohiro KUKI
Tomohiro KUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11950414Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.Type: GrantFiled: November 30, 2020Date of Patent: April 2, 2024Assignee: Kioxia CorporationInventors: Yasuhiro Uchimura, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki, Yasunori Oshima, Osamu Arisumi
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Publication number: 20240090222Abstract: A semiconductor memory device includes a stacked body in which a first insulating layer and a first conductive layer are alternately stacked in a first direction. A columnar body includes a first insulating portion extending in the first direction in the stacked body, a first semiconductor portion provided between the first insulating portion and the stacked body, and a third insulating portion provided between a second insulating portion provided between the first semiconductor portion and the stacked body, and the second insulating portion and the stacked body, and has a first end and a second end opposite to the first end. A second conductive layer is provided on the stacked body and is electrically connected to the first semiconductor portion at the first end of the columnar body.Type: ApplicationFiled: September 1, 2023Publication date: March 14, 2024Inventors: Tatsufumi HAMADA, Yosuke MITSUNO, Tomohiro KUKI, Yusuke MORIKAWA, Ryouji MASUDA, Hiroyasu SATO
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Patent number: 11854971Abstract: A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a first insulating portion and the first conductive layer, a second region between a second insulating portion and the second conductive layer, and a third region between the first region and the second region. The third region includes a fourth region extending in a second direction, a fifth region between the first region and the fourth region, a sixth region between the second region and the fourth region, and a seventh region between the fifth region and the first region and extending in the first direction.Type: GrantFiled: March 3, 2021Date of Patent: December 26, 2023Assignee: KIOXIA CORPORATIONInventors: Yosuke Mitsuno, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki
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Publication number: 20230309303Abstract: A semiconductor memory device includes a substrate, a layer stack, and a pillar. The layer stack is in a first direction above the substrate. The pillar penetrates the layer stack in the first direction. The layer stack includes a first conductor and a first insulator on an upper surface of the first conductor along the first direction. The pillar includes a second insulator extending along an extending direction of the pillar. The second insulator includes a first part located in a first layer in which the first conductor is located and a second part located in a second layer in which the first insulator is located. The first part includes a portion thicker than the second part. A diameter of the pillar in the first layer is larger than a diameter of the pillar in the second layer.Type: ApplicationFiled: September 2, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventors: Yusuke MORIKAWA, Tatsufumi HAMADA, Tomohiro KUKI, Yosuke MITSUNO
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Publication number: 20230292518Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film alternately including first layers and second layers in a first direction, forming a hole extending in the first direction in the stacked film, and forming a first insulator on a side face of the stacked film in the hole. The method further includes removing the first insulator in the hole to expose a first part of the side face of the stacked film at a predetermined height in the first direction of the hole and to expose a side face of the first insulator remaining on a second part of the side face of the stacked film at the predetermined height. The method further includes forming a second insulator on the first part of the side face of the stacked film and the side face of the remaining first insulator in the hole.Type: ApplicationFiled: June 16, 2022Publication date: September 14, 2023Applicant: Kioxia CorporationInventors: Tatsufumi HAMADA, Yosuke MITSUNO, Tomohiro KUKI, Yusuke MORIKAWA
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Patent number: 11721625Abstract: A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a first insulating portion and the first conductive layer, a second region between a second insulating portion and the second conductive layer, and a third region between the first region and the second region. The third region includes a fourth region extending in a second direction, a fifth region between the first region and the fourth region, a sixth region between the second region and the fourth region, and a seventh region between the fifth region and the first region and extending in the first direction.Type: GrantFiled: March 3, 2021Date of Patent: August 8, 2023Assignee: KIOXIA CORPORATIONInventors: Yosuke Mitsuno, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki
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Publication number: 20230093316Abstract: A semiconductor storage device according to an embodiment includes a stacked body and a pillar. The pillar includes an insulating core, a channel layer, and a memory film. A plurality of gate electrode layers included in the stacked body includes a plurality of first gate electrode layers and one or more second gate electrode layers. The channel layer includes a first portion and a second portion. The first portion is provided between an uppermost first gate electrode layer and the insulating core. The second portion extends from a first height to a second height. A film thickness of the second portion is greater than a film thickness of the first portion.Type: ApplicationFiled: March 14, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Tomohiro KUKI, Tatsufumi HAMADA, Shinichi SOTOME, Yosuke MITSUNO
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Patent number: 11587942Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate functioning as a channel of a cell transistor; a first silicon nitride layer above the semiconductor having an internal compressive stress of a first value; and a second silicon nitride layer above the first silicon nitride layer having an internal compressive stress of a second value. The second value is greater than the first value.Type: GrantFiled: August 6, 2020Date of Patent: February 21, 2023Assignee: Kioxia CorporationInventors: Tomohiro Kuki, Tatsufumi Hamada
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Publication number: 20220302138Abstract: A semiconductor storage device includes a first stacked body, a second stacked body, an intermediate insulating layer, and a plurality of columnar bodies. The intermediate insulating layer is located between a first stacked body and a second stacked body and has a thickness in the stacking direction larger than that of one insulating layer in the plurality of insulating layers of the first stacked body. The plurality of columnar bodies are provided over the first stacked body and the second stacked body, and each columnar body includes a semiconductor body, a charge storage film provided between at least one of the plurality of conductive layers and the semiconductor body, and a semiconductor film. Each of the plurality of columnar bodies include a first columnar portion formed in the first stacked body, a second columnar portion formed in the intermediate insulating layer, and a third columnar portion formed in the second stacked body.Type: ApplicationFiled: September 1, 2021Publication date: September 22, 2022Inventors: Yosuke MITSUNO, Tatsufumi HAMADA, Shinichi SOTOME, Tomohiro KUKI
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Publication number: 20220278124Abstract: A semiconductor device includes: a first stacked film including first electrode layers; an insulating layer provided on the first stacked film; a second stacked film provided on the insulating layer and including second electrode layers; and a columnar portion extending through the first stacked film, the insulating layer, and the second stacked film. The columnar portion extending in the insulating layer includes a first portion having a first width in a second direction intersecting the first direction, and a second portion provided at a different location along the first direction and having a second width in the second direction. The columnar portion extending in the second stacked film includes a third portion having a third width along the second direction. The second width is larger than the first width and the third width.Type: ApplicationFiled: August 27, 2021Publication date: September 1, 2022Applicant: Kioxia CorporationInventors: Tatsufumi HAMADA, Tomohiro KUKI, Yosuke MUTSUNO, Shinichi SOTOME, Ryota SUZUKI
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Patent number: 11296111Abstract: According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.Type: GrantFiled: February 25, 2020Date of Patent: April 5, 2022Assignee: KIOXIA CORPORATIONInventors: Yosuke Mitsuno, Tatsufumi Hamada, Shinichi Sotome, Tomohiro Kuki, Yuya Akeboshi
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Patent number: 11282853Abstract: According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.Type: GrantFiled: September 4, 2019Date of Patent: March 22, 2022Assignee: KIOXIA CORPORATIONInventors: Shinichi Sotome, Tatsufumi Hamada, Yasuhiro Uchimura, Tomohiro Kuki
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Publication number: 20220068964Abstract: According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.Type: ApplicationFiled: March 17, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Tomohiro KUKI, Tatsufumi HAMADA, Shinichi SOTOME, Yosuke MITSUNO, Muneyuki TSUDA
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Publication number: 20210366830Abstract: A device includes a first semiconductor layer that includes a first region provided between a first insulating portion and first conductive layers, a second region provided between a second insulating portion and second conductive layers, and a third region provided between the first region and the second region. A first insulating layer includes a thickness (t1) from a surface in the first region to a gate insulating film. The first insulating layer includes a thickness (t2) from a surface in the second region to the gate insulating film. The first insulating layer includes a thickness (t3) from a surface in the third region to the gate insulating film, which is larger than t1-2 nanometers (nm), and larger than t2-2 nm.Type: ApplicationFiled: March 3, 2021Publication date: November 25, 2021Inventors: Yosuke MITSUNO, Tatsufumi HAMADA, Shinichi SOTOME, Tomohiro KUKI
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Publication number: 20210082940Abstract: According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Applicant: Kioxia CorporationInventors: Yasuhiro UCHIMURA, Tatsufumi HAMADA, Shinichi SOTOME, Tomohiro KUKI, Yasunori OSHIMA, Osamu ARISUMI
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Publication number: 20210028189Abstract: According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.Type: ApplicationFiled: February 25, 2020Publication date: January 28, 2021Inventors: Yosuke MITSUNO, Tatsufumi HAMADA, Shinichi SOTOME, Tomohiro KUKI, Yuya AKEBOSHI
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Publication number: 20200381444Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate functioning as a channel of a cell transistor; a first silicon nitride layer above the semiconductor having an internal compressive stress of a first value; and a second silicon nitride layer above the first silicon nitride layer having an internal compressive stress of a second value. The second value is greater than the first value.Type: ApplicationFiled: August 6, 2020Publication date: December 3, 2020Applicant: Toshiba Memory CorporationInventors: Tomohiro KUKI, Tatsufumi Hamada
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Publication number: 20200295036Abstract: According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.Type: ApplicationFiled: September 4, 2019Publication date: September 17, 2020Applicant: Toshiba Memory CorporationInventors: Shinichi Sotome, Tatsufumi Hamada, Yasuhiro Uchimura, Tomohiro Kuki
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Publication number: 20190363101Abstract: According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate; a cell transistor which includes a part formed in the semiconductor; a first silicon nitride layer above the cell transistor; and a second silicon nitride layer above the first silicon nitride layer. The second silicon nitride layer has a characteristic different from that of the first silicon nitride layer.Type: ApplicationFiled: March 6, 2019Publication date: November 28, 2019Applicant: Toshiba Memory CorporationInventors: Tomohiro KUKI, Tatsufumi HAMADA
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Patent number: 10176874Abstract: A storage device includes bit lines including a first bit line and a second bit line, memory units including a first memory string having memory cells connected in series, connected to the first bit line, and a second memory string having memory cells connected in series, connected to the second bit line, word lines each connected in common to a gate of a memory cell in the first string and a gate of a memory cell in the second string, and a controller configured to control voltages applied to the bit lines and the word lines during writing. When writing is performed on a selected memory cell of the first memory string, a first voltage is applied to a selected word line connected to the gate of the selected memory cell while a second voltage higher than a zero voltage is applied to the first bit line.Type: GrantFiled: January 18, 2017Date of Patent: January 8, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tomohiro Kuki, Yasuhiro Shimura