Abstract: Reliability is evaluated in constructing a component based-on application and an application for realizing reliability required can be constructed efficiently. A run-time history such as an occurrence frequency of errors, a recovery time required at error occurrence, and a processing capacity at preventive maintenance is added per software component to a run-time history list having been recoded per execution environment such as an application ID, combined component IDs, and executed hardware ID. From these pieces of information, an interval of performing preventive maintenance recommended per software component during system construction is calculated. By comparing reliability per software component and reliability required for the system, advisability is determined and conformance is evaluated. An execution schedule for preventive maintenance and a processing capability are calculated about the entire component-based application created by combining the software components.

Abstract: A power correction value generating unit determines a power correction value for minimizing an error, from a reference output power value of a carrier multiplexed signal, generating due to peak power suppression under a carrier setting based on the carrier setting relating to either one or both of the number of carrier signals and frequency arrangement, and peak suppression setting. An output power error correcting unit corrects a signal gain before or after the carrier signals are multiplexed, using the power correction value obtained by the power correction value generating unit. In an apparatus performing peak suppression according to an input limitation power of the power amplifier, it is possible to always obtain a desirable transmission (output) power even when the number of carriers or carrier frequency arrangement varies.

Abstract: A processor is arranged to make it possible to specify an instruction for which value prediction is thought to enhance program execution performance and execute the instruction and enhance the accuracy of prediction when carrying out value prediction. The processor is provided with an instruction cache to store instructions to which a value prediction field and a value prediction method field are attached. Prior to or in concurrence with fetching and executing an instruction by its execution unit, the execution result value predicted by a value predictor designated by the contents of the value prediction method field of the instruction is output. Only when the value prediction field contains ‘1,’ the predicted value is stored into the register and used in executing a subsequent instruction. The predicted value for an instruction with its value prediction field containing ‘0’ is nullified.

Abstract: A distortion compensator updating and selecting a distortion compensation coefficient applied to a digital transmission signal so as to reduce the difference between the digital transmission signal and a digital feedback signal is disclosed. The distortion compensator includes a control part that controls the level of an input signal to an analog-to-digital conversion part outputting the digital feedback signal in accordance with the magnitude of the amplitude of the digital transmission signal.

Abstract: A deadlock pre-detection program for making a computer execute a first procedure of making the computer read job logic design information structured of a plurality of process steps including an access step involving an access to any one of a plurality of databases, a second procedure of generating a process route configured of at least two access steps on the basis of the job logic design information, a third procedure of acquiring the first access step and the second access step from the process route, a fourth procedure of judging whether a data base access sequence based respectively on the first step and the second step is a predetermined access sequence or not, and a fifth procedure of notifying of, in the case of judging that the access sequence is not the predetermined access sequence, a purport of deviating from the predetermined access sequence.

Abstract: The high-speed barrier synchronization is completed among multiprocessors by saving overhead for parallel process without addition of a particular hardware mechanism. That is, the barrier synchronization process is performed by allocating the synchronization flag area, on the shared memory, indicating the synchronization point where the execution of each processor for completing the barrier synchronization is completed, updating the synchronization flag area with the software in accordance with the executing condition, and comparing, with each processor, the synchronization flag area of the other processors which takes part in the barrier synchronization.

Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.

Abstract: A control method for a distributed data storage is described. In one example, the method includes loading data at high speed and avoiding massive increases in data transfer time due to redundancy while maintaining high reliability through a redundant system. The method includes maintaining the distributed storage system at a high reliability through dual redundant data storage when storing data into multiple storage units. When loading data from multiple storage units, the method includes restoring all data based on the arriving redundant data without waiting for transfer of the remaining data at the point where either of the redundant data is usually acquired, to achieve high speed data loading.

Abstract: The data-transfer latency of a cache-miss load instruction is shortened in a processor having a cache memory. A load history table wherein a transfer address of the cache-miss load instruction is registered is provided between the processor and a memory system. When access addresses are sequential, a request for hardware prefetch to a successive address is issued and the address is registered into a prefetch buffer. Further, when a cache-miss load request to the successive address is issued, the data are transferred from the prefetch buffer directly to the processor. The system may include multiple simultaneous prefetches and a prefetch variable optimized using software.

Abstract: N shared data registers are provided for N+1 processors, respectively. For allowing all the processors to read the same data from the shared data registers, the processors are connected by interprocessor communication channels. The processors are classified into a master processor and subordinate processors. All data writing into the shared data registers are executed from the master processor. Further, data writing into the shared data registers from the subordinate processor is executed from the master processor after a write request is sent to the master processor.

Abstract: A processor is arranged to make it possible to specify an instruction for which value prediction is thought to enhance program execution performance and execute the instruction and enhance the accuracy of prediction when carrying out value prediction. The processor is provided with an instruction cache to store instructions to which a value prediction field and a value prediction method field are attached. Prior to or in concurrence with fetching and executing an instruction by its execution unit, the execution result value predicted by a value predictor designated by the contents of the value prediction method field of the instruction is output. Only when the value prediction field contains ‘1’ the predicted value is stored into the register and used in executing a subsequent instruction. The predicted value for an instruction with its value prediction field containing ‘0’ is nullified.

Abstract: The data-transfer latency of a cache-miss load instruction is shortened in a processor having a cache memory. A load history table wherein a transfer address of the cache-miss load instruction is registered is provided between the processor and a memory system. When access addresses are sequential, a request for hardware prefetch to a successive address is issued and the address is registered into a prefetch buffer. Further, when a cache-miss load request to the successive address is issued, the data are transferred from the prefetch buffer directly to the processor. The system may include multiple simultaneous prefetches and a prefetch variable optimized using software.

Abstract: Disclosed is a memory system which comprises a first cache memory of a high rank close to a processor; a second cache memory or a main memory device of a lower rank; a first table for storing a line address when there is no line data in the first cache memory at a time of making a transfer request for the line data and the transfer request for the line data is made to the second cache memory or the main memory device; and means for comparing a line address registered in the first table with a line address of a transfer destination every time the transfer request is made. When a result of comparison of the line address in the first table is a miss-hit, the line address of the transfer destination is registered in the first table and it is indicated whether the result of comparison of the line address in the first table is a hit or miss-hit.

Abstract: In a vacuum-operated sewage system, a vacuum sewage pipe (31) evacuated inside to a vacuum state is connected to a sewage suction pipe (15) via a vacuum valve (14) operated by the vacuum in the vacuum sewage pipe (31). While the vacuum valve (14) is open, sewage accumulated in a sewage tank (11) is sucked through the sewage suction pipe (15) into the vacuum sewage pipe (31). An air inlet valve (20) is connected in the neighborhood of the vacuum valve (14) and between the vacuum valve (14) and the vacuum sewage pipe (31), and operated by the vacuum in the vacuum sewage pipe (31). When the degree of vacuum drops in the vacuum sewage pipe (31), the air inlet valve (20) is allowed to open and supply air into the vacuum sewage pipe (31).

Abstract: A radio relay apparatus complying with SDH is provided which permits the value of B2 bytes received from a transmitting-side terminal station to be sent to a receiving-side terminal station even in the case where resetting of a pointer value is performed. B2 sampling means of the radio relay apparatus samples B2 byte information, and B2 recomputing means again performs B2 parity computation of received transmission information which has been subjected to the pointer value resetting. Adding means adds bit by bit the data sampled by the B2 sampling means to the data obtained by the B2 recomputing means, and transmitting means transmits the sum obtained by the adding means to a subsequent radio relay apparatus. Based on the sum transmitted from the transmitting means, the subsequent radio relay apparatus judges that data which is a subject of B2 parity computation and which corresponds to a bit having the value "1" is erroneous.

Abstract: In a feed forward amplifier, an RF amplifier is supplied with an input RF signal at an input terminal for amplifying the same; a distortion extraction loop supplied with the input RF signal and further with the output RF signal from the RF amplifier is for extracting non-linear distortion components formed in the output RF signal as a result of amplification in the RF amplifier; a variable phase shifter is provided in the distortion extraction loop for varying a phase of the input RF signal; a variable attenuator is provided in the distortion extraction loop for attenuating an amplitude of the input RF signal that has been supplied to the distortion extraction loop; and a distortion extraction circuit is provided in the distortion extraction loop for producing a distortion output signal that includes non-linear components; further, a control circuit is supplied with the input signal and with the distortion output signal for extracting a main signal component contained in the distortion output signal.