Patents by Inventor Tomohiro Namise

Tomohiro Namise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10812053
    Abstract: Provided is a transmission device including: a first transmitter that has a plurality of drivers that each enable transmission of a signal using a plurality of voltages including a first voltage, a second voltage, and a third voltage between the first voltage and the second voltage, and that transmits a sequence of symbols; a second transmitter that has a plurality of drivers that each enable transmission of a signal using the plurality of voltages, and that transmits a sequence of symbols; and a voltage generator that generates the third voltage. Each of the drivers of the first transmitter and the drivers of the second transmitter has a switch that transmits the third voltage generated by the voltage generator to an output terminal of the driver through turn-on operation of the switch.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: October 20, 2020
    Assignee: Sony Corporation
    Inventors: Hiroaki Hayashi, Tomohiro Namise
  • Patent number: 10616007
    Abstract: A transmission device according to the disclosure includes: a controller that selects one of a plurality of operation modes; and a first transmitter that includes a first capacitance setting section that sets a load capacitance in accordance with an operation mode selected by the controller, and is configured to be able to output, to a first output terminal, a first signal having a signal format according to the selected operation mode, among a plurality of signal formats.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: April 7, 2020
    Assignee: Sony Corporation
    Inventor: Tomohiro Namise
  • Publication number: 20190028306
    Abstract: A transmission device according to the disclosure includes: a controller that selects one of a plurality of operation modes; and a first transmitter that includes a first capacitance setting section that sets a load capacitance in accordance with an operation mode selected by the controller, and is configured to be able to output, to a first output terminal, a first signal having a signal format according to the selected operation mode, among a plurality of signal formats.
    Type: Application
    Filed: January 16, 2017
    Publication date: January 24, 2019
    Inventor: Tomohiro Namise
  • Publication number: 20110222355
    Abstract: Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 15, 2011
    Applicant: Sony Corporation
    Inventors: Chieko Nakashima, Tomohiro Namise, Tsunenori Shiimoto
  • Patent number: 7023732
    Abstract: The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: April 4, 2006
    Assignee: Sony Corporation
    Inventors: Shunji Sekimoto, Tomohiro Namise
  • Publication number: 20050012139
    Abstract: The present invention is to propose an data erasing method, a memory apparatus, and a data erasing circuit which are able to reduce the time required to boost the potential of the semiconductor substrate thereby to reduce the time required to erase data. Namely, a memory apparatus having a data erasing circuit that erases stored data by applying an erasing voltage between a semiconductor substrate and a control gate so as to discharge electric charges accumulated in a floating gate is disclosed. In this case, the data erasing circuit boosts a potential of the semiconductor substrate side while placing the control gate into its floating state; and applies an erasing voltage between the semiconductor substrate and the control gate to make the potential of the control gate to a predetermined potential.
    Type: Application
    Filed: June 29, 2004
    Publication date: January 20, 2005
    Inventors: Shunji Sekimoto, Tomohiro Namise