Abstract: The invention has been made in view of the above problems, and provides a plasma processing method capable of preventing etching shape abnormality in a plasma processing method for forming a mask layer of a polysilicon film. The invention relates to a plasma processing method for plasma-etching a polysilicon film, the plasma processing method comprising plasma-etching the polysilicon film using a mixed gas including a halogen gas, a fluorocarbon gas, an oxygen gas, and a carbonyl sulfide gas.

Abstract: The invention has been made in view of the above problems, and provides a plasma processing method capable of preventing etching shape abnormality in a plasma processing method for forming a mask layer of a polysilicon film. The invention relates to a plasma processing method for plasma-etching a polysilicon film, the plasma processing method comprising plasma-etching the polysilicon film using a mixed gas including a halogen gas, a fluorocarbon gas, an oxygen gas, and a carbonyl sulfide gas.

Abstract: According to one embodiment a semiconductor memory device includes a first stacked body, a pillar, a memory film, a capacitive element, a first wiring, and a second wiring. The capacitive element includes a first conductive member and a second conductive member. A first length of the first conductive member in a first direction is larger than a second length of the first conductive member in a second direction crossing the first direction. A third length of the first conductive member in a third direction crossing the first direction and the second direction is larger than the second length. A fourth length of the second conductive member in the first direction is larger than a fifth length of the second conductive member in the second direction. A sixth length of the second conductive member in the third direction is larger than the fifth length.

Abstract: According to one embodiment a semiconductor memory device includes a first stacked body, a pillar, a memory film, a capacitive element, a first wiring, and a second wiring. The capacitive element includes a first conductive member and a second conductive member. A first length of the first conductive member in a first direction is larger than a second length of the first conductive member in a second direction crossing the first direction. A third length of the first conductive member in a third direction crossing the first direction and the second direction is larger than the second length. A fourth length of the second conductive member in the first direction is larger than a fifth length of the second conductive member in the second direction. A sixth length of the second conductive member in the third direction is larger than the fifth length.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

Abstract: An upper electrode layer is processed into plural electrode shapes with lithography and subsequent dry etching to pattern plural upper electrodes, followed by conducting an RTA treatment at a treatment temperature of a value in a range from 400° C. to 1000° C. and at an oxygen flow volume of a value in a range from 0.1 L/min to 100 L/min and, subsequently, by conducting an annealing treatment at a treatment temperature of 650° C. in an oxygen atmosphere for 60 minutes.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: There are provided a capacitor lower electrode formed on an adhesive layer, whose surface roughness is 0.79 nm or less, and having a (111) orientation that is inclined from a perpendicular direction to an upper surface of a substrate by 2.3° or less, a ferroelectric layer having a structure the (111) orientation of which is inclined from the perpendicular direction to the upper surface of the substrate by 3.5° or less, and a capacitor upper electrode.

Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).

Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.

Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.

Abstract: A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

Abstract: An upper electrode layer is processed into plural electrode shapes with lithography and subsequent dry etching to pattern plural upper electrodes, followed by conducting an RTA treatment at a treatment temperature of a value in a range from 400° C. to 1000° C. and at an oxygen flow volume of a value in a range from 0.1 L/min to 100 L/min and, subsequently, by conducting an annealing treatment at a treatment temperature of 650° C. in an oxygen atmosphere for 60 minutes.

Abstract: A ferroelectric capacitor including a bottom electrode (15), a ferroelectric film (16) and a top electrode (17) is covered with an interlayer insulating film (18). One end of the bottom electrode (15) is formed like comb teeth. To match with the remaining portion of that end, a plurality of contact holes (21) are formed in the interlayer insulating film (18). In other words, gaps (notches) are formed in the bottom electrode (15) between lower ends of at least two of the contact holes (21). And a wiring (25) connected to the bottom electrode (15) through the contact holes (21) is formed on the interlayer insulating film (18).

Abstract: A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.

Abstract: An interlayer insulating film covering a ferroelectric capacitor is formed, and through the interlayer insulating film, contact holes each reaching a capacitor electrode are formed. A wiring connected to the capacitor electrode through the contact hole is further formed above the interlayer insulating film. A planar shape of the contact hole is a regular octagon, a regular rectangle with four angles thereof being rounded, an octagon with a length of each neighboring side thereof being different to each other, a circle, and so forth.

Abstract: A method of fabricating a ferroelectric capacitor comprises the steps of forming an upper electrode on a ferroelectric film formed on a lower electrode by a sputtering process of a conductive oxide film, wherein the sputtering process is conducted by using a metal target under a first, oxidizing condition and a second, less oxidizing condition.