Abstract: Disclosed herein is a coil component that includes a planar coil pattern having first and a second main surfaces opposite to each other, a first resin layer covering the first main surface of the coil pattern, and a magnetic body covering the second main surface of the coil pattern. The coil pattern includes a terminal part positioned at an end thereof. The first resin layer has a first opening at a part of the terminal part. The magnetic body has a second opening at a part of the terminal part. The first main surface of the terminal part has a first part overlapping the first opening and a second part covered with the first resin layer. The second main surface of the terminal part has a third part overlapping the second opening and a fourth part covered with the magnetic body.

Abstract: A mechanical seal includes: a mating ring; a seal ring; a casing which includes a pop-out regulation portion supporting the seal ring not to be rotatable and to be axially movable and coming into contact with the seal ring to regulate the seal ring from popping out toward the mating ring; an urging member disposed between the seal ring and a back wall of the casing axially overlapping with the seal ring and axially urges the seal ring toward the mating ring; and an annular secondary seal sealing a gap between the casing and the seal ring. The casing includes a regulation wall which regulates the secondary seal from moving toward the side opposite to the mating ring and an axial dimension between the seal ring and the regulation wall is equal to or less than a half of an axial dimension of the secondary seal while the seal ring and the pop-out regulation portion are in contact with each other.

Abstract: A sealing device provides consistent sealing performance in applications where a rotating shaft rotates at high speed. The sealing device 10 seals an annular gap between a rotating shaft 50 and a housing 60, and includes a case 100 fixedly attached to the shaft hole, and a seal ring 200 held in the case 100 such as to be restricted from moving in a rotating direction, and to separate a high-pressure side (H) where pressure rises during use of the sealing device from an opposite low-pressure side (L). The seal ring 200 is disposed such that there is an annular gap between itself and an outer circumferential surface of the rotating shaft 50, and the annular gap is dimensioned such that a fluid pressure of a sealed fluid flowing from the high-pressure side (H) into the low-pressure side (L) causes the Lomakin effect.

Abstract: A mechanical seal includes: a mating ring; a seal ring; a casing which includes a pop-out regulation portion supporting the seal ring not to be rotatable and to be axially movable and coming into contact with the seal ring to regulate the seal ring from popping out toward the mating ring; an urging member disposed between the seal ring and a back wall of the casing axially overlapping with the seal ring and axially urges the seal ring toward the mating ring; and an annular secondary seal sealing a gap between the casing and the seal ring. The casing includes a regulation wall which regulates the secondary seal from moving toward the side opposite to the mating ring and an axial dimension between the seal ring and the regulation wall is equal to or less than a half of an axial dimension of the secondary seal while the seal ring and the pop-out regulation portion are in contact with each other.

Abstract: A determination device (1) includes: an acquisition unit (11) that acquires determination information for determining a degree of deterioration or guarantee of a lead-acid battery (3); a determination unit (11) that determines the degree of deterioration or guarantee of the lead-acid battery (3) by referring to a database (142) that stores the determination information and the degree of deterioration or guarantee of the lead-acid battery (3) in association with each other based on the acquired determination information; and an output unit (11) that outputs a result determined by the determination unit (11).

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are reset to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information.

Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.

Abstract: For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.