Abstract: Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

Abstract: A first timing comparator TCP1 latches a data signal at a timing that corresponds to each edge of a first strobe signal. A first delay element delays a first strobe signal so as to output a first delayed strobe signal. A first clock recovery unit makes a comparison between the phase of the first delayed strobe signal and a clock signal, and outputs a first reference strobe signal which is used to perform phase adjustment such that the phases of these signals match each other. A third delay element delays a first reference strobe signal, and outputs the signal thus delayed as the first strobe signal. A delay amount that corresponds to the amount of skew that occurs between the data signal and the clock signal is set for the third delay element.

Abstract: Provided is a test apparatus that tests a device under test, comprising a clock recovering section that recovers a clock signal from an output signal output by the device under test; an acquiring section that acquires the output signal at a timing corresponding to the clock signal; an adjusting section that adjusts a phase difference between the clock signal and the output signal received by the acquiring section, according to an adjustment amount supplied thereto; a setting memory that stores an adjustment amount of the phase difference between the clock signal and the output signal in the acquiring section in association with each of a plurality of test conditions; and a setting section that supplies the adjusting section with an adjustment amount associated with a test condition for testing the device under test, based on the adjustment amounts stored in the setting memory.

Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing compara

Abstract: There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing compara