Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.

Abstract: A method of manufacturing a semiconductor device wherein semiconductor elements (e.g., transistors) respectively formed in multiple independent wells have the same characteristics with the number of production process steps being reduced. A P-type well as an area of a first conductivity type is formed on a semiconductor substrate. Then, second and fourth wells as two regions of a second conductivity type are formed apart from each other in the P-type well, and a first buried well of N-type as a first buried region of the second conductivity type to connect the second and fourth wells is formed at the bottom of a third well (part of the area of the first conductivity type) sandwiched between the second and fourth wells. In this way, a triple well is formed on the semiconductor substrate.

Abstract: High voltage-resistant semiconductor devices adapted to control threshold voltage by utilizing threshold voltage variation caused by plasma damage resulting from the formation of multilayer wiring, and a manufacturing method thereof. Exemplary high voltage-resistant semiconductor devices include a plurality of MOS transistors having gate insulating films not less than about 350 ? in thickness on a silicon substrate, and the MOS transistors have different area ratios between gate electrode-gate insulating film contact areas and total opening areas of contacts formed on the gate electrodes.