Patents by Inventor Tomohisa AOKI

Tomohisa AOKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955558
    Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Atsushi Hachiya, Hiroaki Furukawa, Yuhichi Saitoh, Tomohisa Aoki
  • Publication number: 20230209893
    Abstract: A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.
    Type: Application
    Filed: May 25, 2020
    Publication date: June 29, 2023
    Inventors: Tomohisa AOKI, ATSUSHI HACHIYA, Yuhichi SAITOH, HIROAKI FURUKAWA
  • Publication number: 20230140018
    Abstract: An array substrate includes a thin film transistor including a drain electrode, a first insulation film included in an upper layer than the drain electrode and including a contact hole overlapping the drain electrode, a pixel electrode included in an upper layer than the first insulation film and overlaps the drain electrode at least inside the contact hole and is connected to the drain electrode, a second insulation film included in an upper layer than the pixel electrode and overlaps the pixel electrode inside the contact hole and extends outside the contact hole, a conductive portion included in an upper layer than the second insulation film and overlaps the pixel electrode at least inside the contact hole, and an insulation portion included in an upper layer than the pixel electrode and in a lower layer than the conductive portion and overlaps the pixel electrode inside the contact hole.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 4, 2023
    Inventors: Tomohisa AOKI, Tsuyoshi ITOH, Tohru SAKATA, Miho YAMADA, Kohichi KUMAGAI
  • Publication number: 20220209021
    Abstract: A crystalline silicon semiconductor layer includes a first channel region and a second conductor region. An oxide semiconductor layer includes a second channel region and a second conductor region. An lower metal layer includes a lower wire. The lower wire is in contact with a first conductor region in a first contact hole. The first conductor region and the second conductor region are electrically connected together through the lower wire.
    Type: Application
    Filed: April 26, 2019
    Publication date: June 30, 2022
    Inventors: HIROAKI FURUKAWA, Yuhichi SAITOH, Tomohisa AOKI, ATSUSHI HACHIYA
  • Publication number: 20220209020
    Abstract: An oxide semiconductor layer includes a second channel region and a second conductor region. The lower metal layer includes a contact wire in contact with the second conductor region. The upper metal layer includes an upper wire. A second interlayer insulating film is provided with a second contact hole overlapping an upper wire and the contact wire. The second conductor region and the upper wire electrically connect together through the contact wire.
    Type: Application
    Filed: April 26, 2019
    Publication date: June 30, 2022
    Inventors: Tomohisa AOKI, HIROAKI FURUKAWA, Yuhichi SAITOH, ATSUSHI HACHIYA
  • Publication number: 20220157996
    Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.
    Type: Application
    Filed: April 26, 2019
    Publication date: May 19, 2022
    Inventors: ATSUSHI HACHIYA, HIROAKI FURUKAWA, Yuhichi SAITOH, Tomohisa AOKI
  • Patent number: 10854756
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 1, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yuhichi Saitoh, Hiroaki Furukawa, Tomohisa Aoki, Atsushi Hachiya
  • Publication number: 20190273167
    Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 5, 2019
    Inventors: Yuhichi SAITOH, Hiroaki FURUKAWA, Tomohisa AOKI, Atsushi HACHIYA