Patents by Inventor Tomohisa Kimura
Tomohisa Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9495494Abstract: The circuit simulating method according to an embodiment includes obtaining a first electrical characteristic value of a circuit element that operates under a predetermined operational condition. The circuit simulating method includes correcting the first electrical characteristic value based on a period in which application of an electrical stress equal to or higher than a reference value is stopped during operation of the circuit element.Type: GrantFiled: March 11, 2015Date of Patent: November 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Kimura, Kazuhide Abe
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Patent number: 9287717Abstract: A power receiving device includes: a plurality of antennas, a plurality of rectenna rectifying circuits each of which is provided to correspond to each of the antennas and each of which converts electromagnetic waves received by the corresponding antenna into DC power and outputs the DC power; a connection switching circuit which is provided between the plurality of rectenna rectifying circuits and a load and which performs switching between serial/parallel connection states of the output side of the plurality of rectenna rectifying circuits; a current sensor which measures current flowing through the load; and a control section which, on the basis of the current measured by the current sensor, selects a serial/parallel connection state of the rectenna rectifying circuits, the state enabling the RF-DC conversion efficiency to be maximized, and which controls the connection switching circuit so that the rectenna rectifying circuits is in the selected serial/parallel connection state.Type: GrantFiled: November 24, 2010Date of Patent: March 15, 2016Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kenichi Amma, Tomohisa Kimura, Nobuhiko Fukuda
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Publication number: 20160070836Abstract: The circuit simulating method according to an embodiment includes obtaining a first electrical characteristic value of a circuit element that operates under a predetermined operational condition. The circuit simulating method includes correcting the first electrical characteristic value based on a period in which application of an electrical stress equal to or higher than a reference value is stopped during operation of the circuit element.Type: ApplicationFiled: March 11, 2015Publication date: March 10, 2016Inventors: Tomohisa Kimura, Kazuhide Abe
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Patent number: 9235666Abstract: A simulation device having an ESD (Electro Static Discharge) protection element has a first parameter file creating unit, a second parameter file creating unit, a parameter file storage storing the parameter files created by the first and second parameter file creating units, a parameter file selector changing a parameter file to be selected from the parameter files stored in the parameter file storage, depending on whether or not operation of the ESD protection element should be verified, a netlist creating unit creating a netlist of the semiconductor circuit utilizing the parameter file selected by the parameter file selector, and a simulation executing unit verifying the operation of the semiconductor circuit based on the netlist.Type: GrantFiled: March 19, 2012Date of Patent: January 12, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Tomohisa Kimura
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Patent number: 9124141Abstract: It is desired to provide a wireless power transmission system which it is possible to more surely prevent the leakage of a microwave. A wireless power transmission system includes: a power transmission antenna configured to output a microwave from an output plane; a power reception antenna arranged in a position opposing to said output plane of said power transmission antenna in power transmission and configured to receive the microwave outputted from said power transmission antenna by an input plane; and a shield section configured to electromagnetically shield a space between said power transmission antenna and said power reception antenna from an external space by a plurality of outer circumference coil springs provided in an area which surrounds said output plane of said power transmission antenna. The coil spring bends along a convex section compared with a wire member when there is the convex section in a hit part. Therefore, good electromagnetic wave shield efficiency is obtained.Type: GrantFiled: June 25, 2010Date of Patent: September 1, 2015Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Kenichi Amma, Katuhito Yamamoto, Yoshiharu Fuse, Tomohisa Kimura, Mamoru Osawa, Hidenori Takasugi
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Publication number: 20130080136Abstract: A simulation device having an ESD (Electro Static Discharge) protection element has a first parameter file creating unit, a second parameter file creating unit, a parameter file storage storing the parameter files created by the first and second parameter file creating units, a parameter file selector changing a parameter file to be selected from the parameter files stored in the parameter file storage, depending on whether or not operation of the ESD protection element should be verified, a netlist creating unit creating a netlist of the semiconductor circuit utilizing the parameter file selected by the parameter file selector, and a simulation executing unit verifying the operation of the semiconductor circuit based on the netlist.Type: ApplicationFiled: March 19, 2012Publication date: March 28, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tomohisa Kimura
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Publication number: 20120306697Abstract: The precision of phase correction is improved. Provided are a detection unit (40) that detects a phase of arrival of a pilot signal at each of antenna panel on the basis of the pilot signal and a reference signal commonly transmitted to each antenna panel; a position specifying unit (51) that specifies a position of each of the antenna panels relative to a reference panel defined as an antenna panel for reference among the plurality of the antenna panels, on the basis of the phase of arrival and an angle of arrival formed between the direction of arrival of the pilot signal and the antenna panel; and a phase-shift setting unit (52) that sets respective phase shifts for the signals radiated from individual antenna elements on the basis of information about the positions of the antenna panels specified by the position specifying unit (51).Type: ApplicationFiled: February 22, 2011Publication date: December 6, 2012Inventors: Tomohisa Kimura, Kenichi Amma, Nobuhiko Fukuda
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Publication number: 20120133216Abstract: To improve RF-DC conversion efficiency even when input power is varied.Type: ApplicationFiled: November 24, 2010Publication date: May 31, 2012Inventors: Kenichi Amma, Tomohisa Kimura, Nobuhiko Fukuda
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Publication number: 20120126631Abstract: It is desired to provide a wireless power transmission system which it is possible to more surely prevent the leakage of a microwave. A wireless power transmission system includes: a power transmission antenna configured to output a microwave from an output plane; a power reception antenna arranged in a position opposing to said output plane of said power transmission antenna in power transmission and configured to receive the microwave outputted from said power transmission antenna by an input plane; and a shield section configured to electromagnetically shield a space between said power transmission antenna and said power reception antenna from an external space by a plurality of outer circumference coil springs provided in an area which surrounds said output plane of said power transmission antenna. The coil spring bends along a convex section compared with a wire member when there is the convex section in a hit part. Therefore, good electromagnetic wave shield efficiency is obtained.Type: ApplicationFiled: June 25, 2010Publication date: May 24, 2012Inventors: Kenichi Amma, Katuhito Yamamoto, Yoshiharu Fuse, Tomohisa Kimura, Mamoru Osawa, Hidenori Takasugi
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Publication number: 20070245274Abstract: An integrated circuit apparatus according to an aspect of the present invention includes: an input portion for inputting information on a physical form relating to a wiring and an element which are desired out of first schematic data as physical form information on the wiring and the element; a schematic data generating portion for generating a wiring symbol and an element symbol including the physical form information based on the physical form information inputted by the input portion and thereby generating second schematic data having the wiring symbol and the element symbol correspondingly to a mask pattern; and a circuit simulation portion for executing a circuit simulation by using the second schematic data.Type: ApplicationFiled: April 11, 2007Publication date: October 18, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Tomohisa Kimura
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Patent number: 7016820Abstract: A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator āsā. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.Type: GrantFiled: March 26, 2001Date of Patent: March 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Kimura, Makiko Okumura
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Publication number: 20010029601Abstract: A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator “s”. The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.Type: ApplicationFiled: March 26, 2001Publication date: October 11, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomohisa Kimura, Makiko Okumura
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Patent number: 6281828Abstract: An analog/digital converter apparatus includes a reference signal generator circuit for generating a reference signal, a comparator section for determining a relationship in level between an input analog signal and the reference signal, and an encoder for converting a comparison result of the comparator section into a digital signal as an output signal. The comparator section has a comparator for comparing the input analog signal with the reference signal and a switching circuit which is interposed between the comparator and each of an input terminal for the input analog signal and a reference signal output terminal for the reference signal and used for switching the input signal lines of the comparator to compensate an equivalent input offset.Type: GrantFiled: March 18, 1999Date of Patent: August 28, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Kimura, Akira Yasuda
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Patent number: 5857178Abstract: A neural network apparatus includes a neural network including at least two neuron layers each having a plurality of neurons and at least one synapse layer having a plurality of synapses each arranged between the neuron layers, each synapse storing a weight value between the neurons and multiplying the weight value with an output value from each of the neurons in the previous-stage neuron layer to output a product to the next-stage neuron layer, a section for causing an error signal between an output from the neural network and a desired output to back-propagate from an output-side neuron layer to an input-side neuron layer of the neural network, a learning control section for updating the weight value in the synapse on the basis of the error signal and the output value from the previous-stage neuron, and a selecting section for selecting a synapse whose weight value is to be updated by the learning control section when the learning control section is to update the weight values of a predetermined number of sType: GrantFiled: June 11, 1997Date of Patent: January 5, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Kimura, Takeshi Shima
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Patent number: 5465474Abstract: A machining apparatus for improving the roundness of a work. The outer circumference of a work is divided into predetermined intervals, and a difference between the radius of that portion of the work after machined and a target radius thereof is detected for each of the intervals. The position of a tool which corresponds to every predetermined rotation angle is corrected on the basis of a detected radius difference at each of the intervals. The path of the tool is interpolation-computed on the basis of the corrected positions. The tool is turned along the interpolated path, so that the work is machined with a high precision.Type: GrantFiled: February 25, 1994Date of Patent: November 14, 1995Assignee: Kabushiki Kaisha Komatsu SeisakushoInventors: Tomohisa Kimura, Akira Ikoma
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Patent number: 5444413Abstract: An operational amplifier circuit includes a differential amplifier having an inverting input, a non-inverting input, and first and second outputs. The differential amplifier is fed by a current source coupled to a power supply voltage. An active load circuit is coupled to the first and second outputs of the differential amplifier and to a ground potential. An additional transistor is provided having a first current-carrying electrode coupled to the first output of the differential amplifier, a second current-carrying electrode coupled to the active load circuit, and an insulated gate electrode coupled to the active load circuit and the second output of the differential amplifier. An inversion amplifier has an input coupled to the second current-carrying electrode of the transistor, and an output, which is fed back through a compensation capacitor to the first output of the differential amplifier.Type: GrantFiled: September 11, 1992Date of Patent: August 22, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Kimura, Tetsuro Itakura