Patents by Inventor Tomohisa Konno

Tomohisa Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150344739
    Abstract: A chemical mechanical polishing aqueous dispersion includes colloidal silica (A), an anionic water-soluble polymer (B), and at least one type of an alkanolamine salt (C) selected from the group consisting of an alkyl sulfate and an alkyl ether sulfate, the chemical mechanical polishing aqueous dispersion having a pH of 1 to 4.
    Type: Application
    Filed: December 11, 2013
    Publication date: December 3, 2015
    Applicant: JSR CORPORATION
    Inventors: Yasutaka KAMEI, Yoshitaka MIYAZAKI, Tatsuya YAMANAKA, Tomohisa KONNO
  • Publication number: 20140011360
    Abstract: A chemical mechanical polishing aqueous dispersion of the invention includes (A) a first water-soluble polymer having a weight average molecular weight of 500,000 to 2,000,000 and including a heterocyclic ring in its molecule, (B) a second water-soluble polymer or its salt having a weight average molecular weight of 1000 to 10,000 and including one group selected from a carboxyl group and a sulfonic group, (C) an oxidizing agent, and (D) abrasive grains, and has a pH of 7 to 12.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 9, 2014
    Applicant: JSR CORPORATION
    Inventors: Yuuji NAMIE, Tomohisa Konno, Masayuki Motonari, Hirotaka Shida, Akihiro Takemura
  • Patent number: 8574330
    Abstract: A chemical mechanical polishing aqueous dispersion of the invention includes (A) a first water-soluble polymer having a weight average molecular weight of 500,000 to 2,000,000 and including a heterocyclic ring in its molecule, (B) a second water-soluble polymer or its salt having a weight average molecular weight of 1000 to 10,000 and including one group selected from a carboxyl group and a sulfonic group, (C) an oxidizing agent, and (D) abrasive grains, and has a pH of 7 to 12.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 5, 2013
    Assignee: JSR Corporation
    Inventors: Yuuji Namie, Tomohisa Konno, Masayuki Motonari, Hirotaka Shida, Akihiro Takemura
  • Patent number: 8524606
    Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: September 3, 2013
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Patent number: 8513127
    Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 20, 2013
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Josephine B. Chang, Leslie Charns, Jason E. Cummings, Michael A. Guillorn, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Patent number: 8507383
    Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: August 13, 2013
    Assignees: International Business Machines Corporation, JRS Corporation
    Inventors: Takashi Ando, Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Patent number: 8497210
    Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 30, 2013
    Assignees: International Business Machines Corporation, JRS Corporation
    Inventors: Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Publication number: 20130005219
    Abstract: A chemical mechanical polishing aqueous dispersion includes (A) silica particles that include at least one functional group selected from the group consisting of a sulfo group or salts thereof, and (B) an acidic compound.
    Type: Application
    Filed: January 17, 2011
    Publication date: January 3, 2013
    Applicant: JSR Corporation
    Inventors: Akihiro Takemura, Kohei Yoshio, Tatsuya Yamanaka, Tomohisa Konno
  • Publication number: 20120083123
    Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.
    Type: Application
    Filed: January 25, 2011
    Publication date: April 5, 2012
    Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Leslie Charns, Jason E. Cummings, Michael A. Guillorn, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Publication number: 20120083125
    Abstract: Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer.
    Type: Application
    Filed: January 25, 2011
    Publication date: April 5, 2012
    Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leslie Charns, John M. Cotte, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lafaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Publication number: 20120083121
    Abstract: Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.
    Type: Application
    Filed: January 25, 2011
    Publication date: April 5, 2012
    Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Publication number: 20120083122
    Abstract: A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface.
    Type: Application
    Filed: January 24, 2011
    Publication date: April 5, 2012
    Applicants: JSR CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leslie Charns, Jason E. Cummings, Lukasz J. Hupka, Dinesh R. Koli, Tomohisa Konno, Mahadevaiyer Krishnan, Michael F. Lofaro, Jakub W. Nalaskowski, Masahiro Noda, Dinesh K. Penigalapati, Tatsuya Yamanaka
  • Publication number: 20090325383
    Abstract: A chemical mechanical polishing aqueous dispersion according to the invention includes (A) 0.1 to 4 mass % of colloidal silica having an average particle diameter of 10 to 100 nm, and (B) 0.1 to 3 mass % of at least one ammonium salt selected from ammonium phosphate, diammonium phosphate, and ammonium hydrogen sulfate, the chemical mechanical polishing aqueous dispersion having a mass ratio (A)/(B) of the component (A) to the component (B) of 1 to 3 and a pH of 4 to 5 and being able to simultaneously polish at least two films that form a polishing target surface and are selected from a polysilicon film, a silicon nitride film, and a silicon oxide film.
    Type: Application
    Filed: February 20, 2008
    Publication date: December 31, 2009
    Applicant: JSR Corporation
    Inventors: Michiaki Andou, Tomohisa Konno
  • Publication number: 20090221213
    Abstract: A chemical mechanical polishing aqueous dispersion of the invention includes (A) a first water-soluble polymer having a weight average molecular weight of 500,000 to 2,000,000 and including a heterocyclic ring in its molecule, (B) a second water-soluble polymer or its salt having a weight average molecular weight of 1000 to 10,000 and including one group selected from a carboxyl group and a sulfonic group, (C) an oxidizing agent, and (D) abrasive grains, and has a pH of 7 to 12.
    Type: Application
    Filed: September 27, 2007
    Publication date: September 3, 2009
    Applicant: JRS CORPORATION
    Inventors: Yuuji Namie, Tomohisa Konno, Masayuki Motonari, Hirotaka Shida, Akihiro Takemura
  • Publication number: 20090088511
    Abstract: The electroless plating solution of the present invention is an electroless plating solution used for selectively forming a protective film on a surface of an exposed wiring in the production of a semiconductor device having a wiring structure, wherein the electroless plating solution includes a cobalt ion, an ion of a second metal other than cobalt, a chelating agent, a reducing agent, a surface active agent and a specific tetraalkylammonium hydroxide, and the surface active agent is selected from the group consisting of a compound represented by the following formula (2a) or (2b), a sulfonic acid type anionic surface active agent, a polyoxyethylene alkyl ether phosphoric ester and a polyoxyalkylene monoalkyl ether, wherein R5 to R8 are each a hydrogen atom or a specific alkyl group, R9 and R10 are each an alkylene group of 2 to 5 carbon atoms, j and k are each independently an integer of not less than 1, and the sum of j and k is 2 to 50.
    Type: Application
    Filed: March 13, 2007
    Publication date: April 2, 2009
    Applicant: JSR CORPORATION
    Inventors: Tomohisa Konno, Taichi Matsumoto
  • Patent number: 7498294
    Abstract: The cleaning composition which comprises organic polymer particles (A) having a crosslinked structure and a surfactant (B) and is used after chemical mechanical polishing. The cleaning method of a semiconductor substrate is a method for cleaning semiconductor substrate given after chemical mechanical polishing, by the use of the cleaning composition. The process for manufacturing a semiconductor device including a step of chemically and mechanically polishing a semiconductor substrate and a step of cleaning the semiconductor substrate obtained after the chemical mechanical polishing, by the cleaning method.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: March 3, 2009
    Assignee: JSR Corporation
    Inventors: Tomohisa Konno, Kiyonobu Kubota, Masayuki Hattori, Nobuo Kawahashi
  • Publication number: 20080274620
    Abstract: A chemical mechanical polishing method of the present invention comprises conducting polishing by the use of a chemical mechanical polishing aqueous dispersion (A) containing abrasive grains and then conducting polishing by the use of a chemical mechanical polishing aqueous composition (B) containing at least one organic compound having a heterocyclic ring in addition to the chemical mechanical polishing aqueous dispersion (A). Also A chemical mechanical polishing agent kit of the present invention comprises the chemical mechanical polishing aqueous dispersion (A) and the chemical mechanical polishing aqueous composition (B). The polishing method and the polishing agent kit can prevent an increase of dishing and corrosion of wiring portion to enhance the yield.
    Type: Application
    Filed: June 30, 2008
    Publication date: November 6, 2008
    Applicant: JSR CORPORATION
    Inventors: Hirotaka SHIDA, Tomohisa Konno, Masayuki Hattori, Nobuo Kawahashi
  • Patent number: 7378349
    Abstract: Disclosed is a chemical mechanical polishing aqueous dispersion comprising (A1) first fumed silica having a specific surface area of not less than 10 m2/g and less than 160 m2/g and an average secondary particle diameter of not less than 170 nm and not more than 250 nm and (A2) second fumed silica having a specific surface area of not less than 160 m2/g and an average secondary particle diameter of not less than 50 nm and less than 170 nm. Also disclosed is a chemical mechanical polishing method using the chemical mechanical polishing aqueous dispersion. According to the chemical mechanical polishing aqueous dispersion and the chemical mechanical polishing method, a chemical mechanical polishing process wherein a barrier metal layer and a cap layer can be efficiently removed by polishing and damage to an insulating film material of a low dielectric constant present in the underlying layer is reduced can be carried out.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: May 27, 2008
    Assignee: JSR Corporation
    Inventors: Tomohisa Konno, Hirotaka Shida, Kiyonobu Kubota, Masayuki Hattori, Nobuo Kawahashi
  • Publication number: 20080045016
    Abstract: A cleaning composition can decontaminate a surface of a chemically mechanically polished semiconductor substrate having a metal wiring and a low dielectric constant film and can highly remove impurities such as residual abrasive grains, residual polishing waste, and metal ions on the metal wiring and low dielectric constant film without corroding the metal wiring, degrading electric characteristics of the low dielectric constant film, and causing mechanical damage to the low dielectric constant film. A cleaning method of a semiconductor substrate uses the cleaning composition, and a manufacturing method of a semiconductor substrate includes a step of performing the cleaning method. The cleaning composition is used for a chemically mechanically polished surface, and includes organic polymer particles (A) having a crosslinked structure and an average dispersed particle diameter of 10 nm or more and less than 100 nm, and a complexing agent (B).
    Type: Application
    Filed: August 3, 2007
    Publication date: February 21, 2008
    Applicants: JSR CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Michiaki Andou, Tomohisa Konno, Hirotaka Shida, Kazuhito Uchikura, Nobuyuki Kurashima, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano
  • Patent number: 7183211
    Abstract: The object of the present invention is to provide a process for chemical mechanical polishing of semiconductor substrate that is particularly useful for chemical mechanical polishing a wafer having a wiring pattern and an insulating layer having a low dielectric constant is formed between wiring patterns, interlayers in the case of a multi-layer wiring and the like in the process of producing a semiconductor device, and an aqueous dispersion for chemical mechanical polishing which is used in this process.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: February 27, 2007
    Assignee: JSR Corporation
    Inventors: Tomohisa Konno, Masayuki Motonari, Masayuki Hattori, Nobuo Kawahashi