Abstract: A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell.

Abstract: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.

Abstract: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.

Abstract: A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.

Abstract: A planetary gear set including a plurality of pinions meshing with a sun gear and a carrier C that shaft-supports the pinions. The carrier has an annular peripheral wall that extends entirely around outer peripheries of the plurality of pinions. Thin-wall portions receded at a radially inner side are formed in the annular peripheral wall, at circumferential-direction positions corresponding to the positions of the pinions.

Abstract: A planetary gear set comprises a plurality of pinions P1, P2 meshing with a sun gear, and a carrier C that shaft-supports the pinions. The carrier has an annular peripheral wall 12 that extends entirely around outer peripheries of the plurality of pinions. Thin-wall portions 12a receded at a radially inner side are formed in the annular peripheral wall, at circumferential-direction positions corresponding to the positions of the pinions. The circumferential continuity of the annular peripheral wall secures a carrier rigidity. The formation of the thin-wall portions avoids interference between each pinion and the annular peripheral wall without involving an increased diameter of the carrier. The pinions P1 have a smaller diameter than the pinions P2. A platy wall portion 32 of a bridge portion 3 extends in the direction of a circumference of the carrier, outwardly of the pinions P1.

Abstract: 2'-Deoxy-3',5'-di-O-alkylcarbonyl-5-fluorouridine derivatives possessing strong anti-tumor activity with weak toxicity and represented by the general formula: ##STR1## wherein R stands for an alkyl group, an alkoxy group or a halogen atom, m for zero or an integer of 1-3, and n for an integer of 1-14, with the proviso that when m is 2 or 3, R's may be the same or different and that when m is 2 and the adjacent two R's are alkoxy groups, the two alkyl moieties of the alkoxy groups may be combined to form together with the two adjacent oxa bridging members an alkylenedioxy group as a whole. These derivatives are prepared by acylating a 2'-deoxy-3',5'-di-O-alkylcarbonyl-5-fluorouridine with corresponding benzoyl halides and are useful as active ingredients for anti-tumor agents, especially for oral administration.

Abstract: New ester derivatives of alkoxybenzoyldeoxyfluorouridine of the general formula ##STR1## wherein R stands for an alkoxy group having 1 to 4 carbon atoms, m for 1 or 2, and n for 3 or 4 with the proviso that when m is 2, the adjacent two R's may be combined to form an alkylenedioxy group as a whole. These derivatives are prepared by acylating a 2'-deoxy-3',5'-di-O-alkylcarbonyl-5-fluorouridine with corresponding benzoyl halides and are useful as active ingredients for anti-tumor agents, especially for oral administration.

Abstract: New ester derivatives of deoxyfluorouridine of the general formula: ##STR1## wherein R and R.sup.40, may be identical or different, and may be hydrogen, halogen or methyl and n is 3 or 4. These derivatives are prepared by acylating a 2'-deoxy-3',5'-di-O-alkylcarbonyl-5-fluorouridine with corresponding benzoyl halides and are useful as active ingredients for anti-tumor agents, especially for oral administeration.

Abstract: A process for the preparation of 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol (i.e. ifenprodil) and acid-addition salts thereof, characterized by brominating 4'-hydroxypropiophenone in a single or mixed solvent selected from the group consisting of methanol, ethanol and a saturated aliphatic ether, removing hydrogen bromide formed in the course of the bromination, adding 4-benzylpyridine to the reaction mixture, heating the reaction mixture under reflux in a single or mixed solvent selected from the group consisting of methanol and ethanol, and then subjecting the resultant reaction mixture to catalytic reduction to form 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol hydrobromide in the reaction mixture. The end product (i.e.