Abstract: The invention is intended to form, on an insulating layer, a thin SiGe layer serving as an underlying layer for obtaining a strained silicon layer, and to provide a satisfactory strained Si layer. A SiGe layer 13 is formed on a Si substrate 11 and an oxygen ion implantation is effected with ensuring the detainment within the layer thickness of the SiGe layer 13. The SiGe layer 13 is lattice-relaxed by a heat treatment and a buried insulating layer 15 is formed simultaneously in the SiGe layer 13. A strained Si layer 17 is re-grown on the lattice-relaxed SiGe layer 13.

Abstract: The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.

Abstract: A semiconductor device having a MISFET includes: a silicon substrate (2) having a semiconductor region on a surface thereof; a source region (10a) and a drain region (10b) formed in the semiconductor region separately; a channel region formed in the semiconductor region and between the source region and the drain region; a gate electrode (6) formed on the channel region; and a region (8a) formed of Si.sub.1-x C.sub.x overlapping the source region and having a carbon concentration enough to increase an energy gap therein beyond that in the channel region. Further, the MISFET is constructed in such a way that a hetero-junction surface formed between the region formed of Si.sub.1-x C.sub.x (8a) and the other portion of the semiconductor region on the side of the channel region exists at an interface between the source region (10a) and the channel region or in the vicinity thereof, in order to realize a high speed operation, even if the device is microminiaturized.

Abstract: An MOS field effect transistor is of a lightly doped drain structure. In the transistor, an insulation layer is located on the side wall of a gate electrode. This insulation layer is formed of tantalum oxide, which has a high dielectric constant. Between this insulation layer and a drain region, another insulation layer is formed such that it has a thickness sufficiently greater than the length of the mean free path of the hot carriers which are generated in the vicinity of the drain region.

Abstract: An MOSFET has the essential feature lying in that the depths of well regions are different between a channel region and a diffusion region under a gate electrode to suppress charges in depletion layers. The MOSFET comprises a first well region which is formed in the channel region of a substrate below a gate electrode, and has a PN junction shallower than the sum of the width of a channel depletion layer formed by a voltage applied to the gate electrode and the width of a depletion layer formed by a substrate voltage of the substrate, and a second well region which is formed in source and drain regions to extend to the first well region, and has a PN junction deeper than the sum of the width of a depletion layer formed in the source or drain region and the width of a depletion layer formed in the first well region by the substrate voltage of the substrate.

Abstract: At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

Abstract: At the surface of a p-type silicon substrate, n-type source/drain diffused layers are formed. On the substrate between the source/drain diffused layers, a gate insulating film made of a silicon oxide film is formed so as to be isolated from the diffused layers. A gate electrode is formed on the gate insulating film. Sidewalls are formed on the sides of the gate insulating film and gate electrode, extending upward from the substrate. In this invention, the sidewalls are composed of material whose permittivity is higher than that of the gate insulating film, for example, of a silicon nitride film.

Abstract: According to the present invention, a lower electrode is formed on a semiconductor substrate and overgrows upward to form one electrode of a capacitor having a mushroom-shaped section. An insulation film is formed so as to at least cover the lower electrode. An upper electrode is formed so as to oppose the lower electrode and to cover at least the insulation film.

Abstract: According to the present invention, a control gate is formed on an n-type Si substrate, and a p-type source-drain region is formed in the surface of the substrate on both the sides of the control gate. A p-type Si.sub.x Ge.sub.1-x (0.ltoreq.x<1) layer and an Al electrode are sequentially formed in the source-drain region. The energy difference between the valence band of the SiGe layer and a vacuum level is smaller than the energy difference between the valence band of an Si layer constituting the source-drain region and the vacuum level, and the energy difference of the conduction band of the SiGe layer and the vacuum level is larger than the energy difference of the conduction band of the Si layer and the vacuum level. For this reason, a Schottky barrier height is decreased, and resistances between the semiconductor layers and the Al electrode are reduced.

Abstract: On a semiconductor substrate are formed a plurality of pedestal regions which are of the same conductivity type as the semiconductor substrate. Insulating layers are formed on side surfaces of the pedestal regions. On the insulating layers are formed gate electrodes which are connected together. First and second regions are formed within top portions of the pedestal regions and the semiconductor substrate. The first and second regions serve as source/drain regions and are of the opposite conductivity type to the semiconductor substrate. The first regions, the second regions and the gate electrodes function to form a single transistor because the gate electrodes are connected together.

Abstract: Disclosed is a MOS type semiconductor device, particularly, a MOS type transistor of an LDD structure, which is featured in the side wall structure which covers the side surface of a gate electrode formed on the surface of a semiconductor substrate with a first insulating film interposed therebetween. The semiconductor device comprises source and drain regions of a double diffusion structure consisting of an impurity diffusion region of a relatively low impurity concentration formed apart from the gate electrode in the surface region of the semiconductor substrate and positioned below the side wall region of the gate electrode, and an impurity diffusion region of a relatively high impurity concentration formed in the surface region of the semiconductor substrate and positioned outside the gate electrode.