Patents by Inventor Tomohisa Okuno

Tomohisa Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220018114
    Abstract: Provided is a portable facility (1) including: a power generation unit (3) and a function unit (5), wherein the power generation unit (3) includes a transportable first housing (H1) and at least one power generation device attached to the first housing (H1), the first housing including a top wall (15), a bottom wall (17), and a surrounding wall (19), the at least one power generation device being one or more of a wind power generation device (7), a solar power generation device (9), and a hydraulic power generation device, and the function unit (5) includes a transportable second housing (H2) and an electric apparatus (11) disposed inside the second housing (H2) and configured to be powered by the power generation unit (3) to operate, the second housing including a top wall (15), a bottom wall (17), and a surrounding wall (19).
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Applicant: NTN CORPORATION
    Inventors: Mitsuru AKAGAWA, Ryosuke KARASAWA, Tomohisa OKUNO, Kaname NISHIMURA
  • Publication number: 20210222676
    Abstract: Provided is a vertical axis wind power generation device including a wind turbine of a vertical axis type including a support column, a main shaft disposed on an upper portion of the support column so as to be rotatable, a plurality of blades coupled to the main shaft through arms; a power generator; and a container having a standard dimension for freight transport. The wind turbine is accommodatable in a folded or disassembled state in the container together with the power generator. The container is provided with a support-column fixing part configured to fix the support column of the wind turbine to the container. The container may include an inclining mount inside the container, the inclining mount being configured to accommodate a folded body of the wind turbine.
    Type: Application
    Filed: April 8, 2021
    Publication date: July 22, 2021
    Applicant: NTN CORPORATION
    Inventors: Ryosuke KARASAWA, Tomohisa OKUNO, Mitsuru AKAGAWA, Kaname NISHIMURA
  • Patent number: 7711012
    Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: May 4, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Tomohisa Okuno, Akihide Shibata, Seizo Kakimoto
  • Patent number: 7057417
    Abstract: By using a first delay circuit that delays by a predetermined time a reference pulse signal having a constant pulse width and a second delay circuit that delays by an arbitrary time the output signal of the first delay circuit, a voltage conversion circuit generates an output pulse signal having a variable pulse period, and varies its output voltage according to the pulse period of this output pulse signal.
    Type: Grant
    Filed: January 21, 2002
    Date of Patent: June 6, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomohisa Okuno
  • Patent number: 6943533
    Abstract: A voltage conversion circuit alternately controls ON/OFF of a PMOS transistor and an NMOS transistor that are provided in series between high voltage power source lines, and outputs a low voltage obtained by causing a filter circuit to smooth an output voltage of each transistor. Further, the voltage conversion circuit uses the output voltage of the filter circuit as a power source of an output pulse signal generating circuit for driving the two transistors. Further, the voltage conversion circuit causes a start-up signal generating circuit to generate a start-up signal for forcing the PMOS transistor to turn ON during a predetermined period on start-up, and causes a switch control circuit to select the start-up signal instead of the pulse signal from the output pulse signal generating circuit, thereby realizing sure start-up.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: September 13, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomohisa Okuno
  • Patent number: 6885229
    Abstract: A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: April 26, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomohisa Okuno, Yuichi Sato
  • Publication number: 20040145925
    Abstract: A voltage conversion circuit alternately controls ON/OFF of a PMOS transistor and an NMOS transistor that are provided in series between high voltage power source lines, and outputs a low voltage obtained by causing a filter circuit to smooth an output voltage of each transistor. Further, the voltage conversion circuit uses the output voltage of the filter circuit as a power source of an output pulse signal generating circuit for driving the two transistors. Further, the voltage conversion circuit causes a start-up signal generating circuit to generate a start-up signal for forcing the PMOS transistor to turn ON during a predetermined period on start-up, and causes a switch control circuit to select the start-up signal instead of the pulse signal from the output pulse signal generating circuit, thereby realizing sure start-up.
    Type: Application
    Filed: January 16, 2004
    Publication date: July 29, 2004
    Inventor: Tomohisa Okuno
  • Publication number: 20040070434
    Abstract: By using a first delay circuit that delays by a predetermined time a reference pulse signal having a constant pulse width and a second delay circuit that delays by an arbitrary time the output signal of the first delay circuit, a voltage conversion circuit generates an output pulse signal having a variable pulse period, and varies its output voltage according to the pulse period of this output pulse signal.
    Type: Application
    Filed: July 25, 2003
    Publication date: April 15, 2004
    Inventor: Tomohisa Okuno
  • Publication number: 20040065901
    Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block (1) is provided with an input/output circuit (2). A transmission line (3) and a branch line (4) connect the input/output circuits (2) so that information can be exchanged through the input/output circuits (2) between one basic circuit block (1) and another basic circuit block (1). The memory in each basic circuit block (1) or in each input/output circuit (2) can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.
    Type: Application
    Filed: August 12, 2003
    Publication date: April 8, 2004
    Inventors: Hiroshi Iwata, Tomohisa Okuno, Akihide Shibata, Seizo Kakimoto
  • Publication number: 20040004509
    Abstract: A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.
    Type: Application
    Filed: June 25, 2003
    Publication date: January 8, 2004
    Inventors: Tomohisa Okuno, Yuichi Sato
  • Patent number: 6617898
    Abstract: A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: September 9, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomohisa Okuno, Yuichi Sato
  • Publication number: 20020084809
    Abstract: A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.
    Type: Application
    Filed: November 13, 2001
    Publication date: July 4, 2002
    Inventors: Tomohisa Okuno, Yuichi Sato
  • Patent number: 6105114
    Abstract: A two-dimensional array transposition circuit having a small circuit scale and accordingly having a small power consumption includes a memory cell array capable of storing a two-dimensional array and an address translation circuit receiving an address signal and generating a row address signal and a column address signal for specifying a memory cell of the memory cell array via a row decoder and a column decoder. The address translation circuit generates, when one two-dimensional array is written into the memory cell array, a row address signal and a column address signal successively such that an order of writing is according to one of an order giving priority to a row direction and selecting a memory cell and an order giving priority to a column direction and selecting a memory cell and generates, when the two-dimensional array is read from the memory cell array, a row address signal and a column address signal successively such that an order of reading is according to the other order.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Tomohisa Okuno