Abstract: A semiconductor device includes a chip mounting portion and a semiconductor chip provided on the chip mounting portion via a conductive adhesive material. Here, a planar shape of the semiconductor chip is a quadrangular shape. Also, in plan view, a plurality of thin portions is formed at a plurality of corner portions of the semiconductor chip, respectively. Also, the plurality of thin portions respectively formed at the plurality of corner portions of the semiconductor chip is spaced apart from each other. Further, thickness of each of the plurality of thin portions is smaller than a thickness of the semiconductor chip other than the plurality of the thin portions.

Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.

Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.

Abstract: A structure analysis apparatus (1) for analyzing structure of a complex material layer containing a plurality of members (2a, 2b) for modeling layout data on a complex material layer, includes: an area setting portion (21) for setting an area to be modeled in the complex material layer; an area dividing portion (22) for dividing the area into a plurality of elements; an area computing portion (23) for calculating, based on an occupancy of each of the plurality of members (2a, 2b) in the area, the number of elements corresponding respectively to the plurality of members (2a, 2b); and an element placing portion (24) for generating a model of the complex material layer by placing the plurality of members (2a, 2b) respectively in the plurality of elements based on the number of the elements corresponding respectively to the plurality of members (2a, 2b).

Abstract: A structure analysis apparatus (1) for analyzing structure of a complex material layer containing a plurality of members (2a, 2b) for modeling layout data on a complex material layer, includes: an area setting portion (21) for setting an area to be modeled in the complex material layer; an area dividing portion (22) for dividing the area into a plurality of elements; an area computing portion (23) for calculating, based on an occupancy of each of the plurality of members (2a, 2b) in the area, the number of elements corresponding respectively to the plurality of members (2a, 2b); and an element placing portion (24) for generating a model of the complex material layer by placing the plurality of members (2a, 2b) respectively in the plurality of elements based on the number of the elements corresponding respectively to the plurality of members (2a, 2b).

Abstract: In one embodiment, provided is a semiconductor device including a first semiconductor package, a second semiconductor package and a conductive plate. The first semiconductor package includes a first interconnect substrate and a first semiconductor chip. The second semiconductor package includes a second interconnect substrate and a second semiconductor chip, and is stacked on the first semiconductor package. The conductive plate is provided between the first semiconductor package and the second semiconductor package. The conductive plate is electrically coupled to the GND plane of the mounting board, so that a fixed potential is provided. The distance from the lower surface of the first interconnect substrate to the lower surface of the second interconnect substrate is larger than a total of a thickness of the first interconnect substrate, a thickness of the first semiconductor chip and a thickness of the conductive plate.