Abstract: A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string.

Abstract: States of LSI internal signals (100 to 107) are monitored. Signal name information (31), signal state information (32), and information (33) about time in an LSI when a signal undergoes a state transition, are packetized and output as trace information (10) to the outside. In a development supporting device, the trace information (10) is decoded, the time information of the LSI is converted into real-time information, and based on the resultant information, a waveform of an LSI internal signal is reproduced. A plurality of LSI internal signals can be traced using terminals (16) the number of which is smaller than the number of the signals to be traced.

Abstract: A debugging system which can efficiently obtain debugging information and which has excellent debugging efficiency is a debugging system which stops execution of a program executed in a program executing apparatus, at a break point, and assists debugging of the program, and which includes: a dump control unit configured to dump information indicating an operating state of the program executing apparatus, at plural points in time prior to the stopping of the execution of the program; and a dump information accumulating unit configured to accumulate the information indicating the operating state of the program executing apparatus dumped by said dump control unit.

Abstract: A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n?1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.

Abstract: A scan test circuit is provided with a scan chain having n pieces of scan storage elements (n: integer, n>1); a scan clock generation circuit which is able to control a frequency of a first clock to be used for shifting data into the first to (n>1)th scan storage elements, and a frequency of a second clock to be used for shifting data into the n-th scan storage element and performing actual operation, independently from each other; and a scan selection internal signal generation circuit for generating a scan selection internal signal that is synchronized with the second clock.