Abstract: A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.

Abstract: A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.

Abstract: A programmable logic device comprises a data storage circuit for storing 1-bit control data and a MOS transistor which is switch controlled in accordance with stored data in the data storage circuit. When the MOS transistor is switch controlled, the power supply voltage of the data storage circuit is raised. Two signal lines are connected with each other through the MOS transistor which has been rendered conductive, thereby permitting a signal to be transmitted between the signal lines.

Abstract: A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

Abstract: In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

Abstract: A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

Abstract: An integrated circuit device includes complementary MOS circuit elements formed in an N type semiconductor substrate with a P type region formed in the substrate. Protective circuit elements connected to an input terminal are formed in an area of the substrate other than the region thereof having the complementary MOS circuit elements formed therein. At least one of the regions constituting the protective circuit elements is formed in a P type additional region formed in the area of the N type substrate.

Abstract: An integrated circuit for a programmable television receiver comprises a memory for storing a plurality of programs, a digital clock and a character generating circuit for generating character signals for displaying the programs in the memory and/or time of the digital clock on the screen of a television receiver. The integrated circuit uses dynamic circuits to reduce the number of elements required, and CMOS transistors to attain a lower power dissipation.

Abstract: An n scale counter includes a shift register having X number of unit delay circuits connected in series and each consisting of a plurality of insulated gate field effect transistors. The unit delay circuits of the shift register are simultaneously supplied with pulses to be counted and each of the delay cicuits is set or reset to an initial state. There is also provided a closed loop circuit including a first gate circuit connected to receive an output signal from the last stage delay circuit as one input terminal, and a logic circuit connected to receive output signals from the first gate circuit and, for example, the first stage delay circuit and produce to the input terminal of the first stage delay circuit an output signal indicating coincidence or incoincidence of its input signals. The counter is capable of counting pulses of (2.sup.x -1) at maximum.